report_05-07-2025_03-33-05.html

Report generated on 07-May-2025 at 03:54:12 by pytest-html v3.2.0

Summary

1916 tests ran in 1266.90 seconds.

758 passed, 0 skipped, 1158 failed, 0 errors, 0 expected failures, 0 unexpected passes

Results

Result Test TIDL Subgraphs Complete TIDL Offload Duration Links
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1742] 1 False 15.49
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1742'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1742', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3104924 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.39863s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.39868s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.39870s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.39874s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.39877s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.39894s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.39905s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1470] 1 False 9.45
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1470'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1470', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3104928 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.57214s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.57224s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.57226s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.57228s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.57231s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.57244s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.57254s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_628] 1 False 20.55
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_628'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_628', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3104939 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:46.230822040 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1398] 1 False 14.51
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1398'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1398', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3104937 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.40490s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.40498s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.40500s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.40503s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.40506s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.40521s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.40526s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_759] 1 False 23.01
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_759'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_759', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3104930 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1612] 1 False 21.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1612'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1612', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3104917 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] 0.82210s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.82227s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.82231s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.82235s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.82245s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.82265s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.82340s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1030] 1 False 10.45
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1030'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1030', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3104919 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:36.123992677 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_723] 1 False 9.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_723'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_723', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3104936 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1725] 1 False 22.69
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1725'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1725', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3104934 parent=3103513 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.60570s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60577s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60579s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60581s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60584s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60594s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60600s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_758] 1 False 9.61
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_758'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_758', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3104927 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1757] 1 False 15.01
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1757'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1757', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3104933 parent=3103460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.250s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.33179s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.33185s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.33187s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.33189s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.33193s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.33203s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.33207s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1693] 1 False 16.65
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1693'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1693', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3104921 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:42.364065729 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1775] 1 False 23.08
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1775'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1775', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3104922 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:48.839587940 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1533] 1 False 9.77
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1533'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1533', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3104938 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1606] 1 False 18.69
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1606'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1606', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3106429 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1042] 1 False 16.77
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1042'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1042', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3106496 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3773s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3788s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:52.733136193 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1869] 1 False 12.70
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1869'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1869', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3106562 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:49.172807817 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1839] 1 False 14.80
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1839'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1839', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3106592 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:51.372388153 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1617] 1 False 10.93
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1617'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1617', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3106644 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3082s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:47.599145971 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_933] 1 False 13.62
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_933'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_933', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3107185 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:54.098329062 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1181] 1 False 24.54
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1181'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1181', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3107503 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:05.671016996 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1712] 1 False 15.73
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1712'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1712', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3107729 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:33:57.834720929 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1343] 1 False 15.26
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1343'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1343', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3107812 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_854] 1 False 21.06
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_854'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_854', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3108122 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:06.551418292 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1686] 1 False 16.09
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1686'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1686', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3108533 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:03.504022745 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1913] 1 False 19.92
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1913'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1913', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3108929 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:08.221659579 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_893] 1 False 17.12
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_893'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_893', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3109011 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:05.849219038 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1624] 1 False 14.11
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1624'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1624', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3109066 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8224s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1340] 1 False 15.01
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1340'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1340', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-2' pid=3109065 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.33455s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.33498s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.33501s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.33505s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.33512s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.33535s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.33548s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.80338s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.80422s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.80433s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1907] 1 False 18.76
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1907'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1907', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3109183 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:07.965692923 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1075] 1 False 12.13
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1075'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1075', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3109889 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.572s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:03.224859437 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_783] 1 False 10.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_783'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_783', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3110018 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:01.849202596 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1117] 1 False 23.51
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1117'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1117', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3110420 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:16.385272620 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1327] 1 False 11.41
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1327'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1327', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-3' pid=3110685 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.497246s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.497273s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.497276s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.497279s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.497288s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.497311s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.497323s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.546268s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.546299s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.546309s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1570] 1 False 12.03
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1570'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1570', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-3' pid=3110691 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_863] 1 False 13.83
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_863'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_863', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3111535 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.583s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:12.030986908 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1274] 1 False 16.36
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1274'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1274', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3112111 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:18.270425436 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1419] 1 False 8.90
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1419'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1419', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-3' pid=3112523 parent=3104035 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.56907s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.56921s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.56923s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.56926s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.56931s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.56954s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.56969s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1082] 1 False 20.39
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1082'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1082', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3112703 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:23.904328678 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1642] 1 False 18.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1642'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1642', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3113050 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:22.303612293 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1938] 1 False 10.51
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1938'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1938', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3113724 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:16.133309659 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1333] 1 False 18.10
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1333'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1333', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-3' pid=3113919 parent=3103899 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3116s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.790105s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.790150s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.790153s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.790156s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.790165s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.790194s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.790212s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.838001s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.838140s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.838154s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1112] 1 False 20.90
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1112'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1112', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3113926 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6107s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:26.747527327 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1367] 1 False 12.43
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1367'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1367', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3114038 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7867s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7887s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:18.063592439 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1645] 1 False 14.38
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1645'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1645', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3114135 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4223s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:20.736902812 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_708] 1 False 19.02
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_708'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_708', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3114431 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:27.053573525 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1308] 1 False 13.72
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1308'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1308', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-4' pid=3114522 parent=3103355 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7899s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7931s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 4.518421s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 4.518442s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 4.518445s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 4.518447s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 4.518453s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 4.518472s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 4.518486s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 4.579401s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 4.579436s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 4.579440s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1666] 1 False 19.35
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1666'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1666', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3114798 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4209s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:29.712711757 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1751] 1 False 10.71
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1751'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1751', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3115093 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1151] 1 False 15.01
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1151'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1151', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3115103 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:27.127462399 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1608] 1 False 12.07
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1608'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1608', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3115164 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_871] 1 False 14.97
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_871'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_871', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3115913 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.391s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:29.582488823 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1733] 1 False 8.23
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1733'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1733', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-5' pid=3116255 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3705s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1072] 1 False 21.44
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1072'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1072', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3116700 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:39.995278378 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1337] 1 False 19.02
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1337'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1337', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-5' pid=3117089 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4188s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:39.331559354 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1750] 1 False 14.34
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1750'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1750', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-4' pid=3117231 parent=3103797 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.50819s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.50830s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.50834s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.50837s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.50844s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.50864s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.50873s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1649] 1 False 12.66
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1649'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1649', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3117634 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:35.010765379 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_944] 1 False 13.56
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_944'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_944', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3117716 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:36.166504021 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1254] 1 False 22.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1254'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1254', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3118166 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9152s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:46.415740769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_912] 1 False 11.97
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_912'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_912', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3118230 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8821s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:35.970472437 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1476] 1 False 15.80
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1476'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1476', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-5' pid=3119061 parent=3103347 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.63630s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.63648s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.63651s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.63653s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.63657s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.63673s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.63683s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:41.732307322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1516] 1 False 19.12
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1516'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1516', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-5' pid=3119093 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1411] 1 False 13.12
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1411'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1411', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3119227 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1303] 1 False 20.79
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1303'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1303', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3119260 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3127s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:47.838015040 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1263] 1 False 24.29
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1263'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1263', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3119368 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:51.680979416 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_958] 1 False 15.80
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_958'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_958', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3120093 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:45.603461594 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1226] 1 False 15.79
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1226'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1226', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3120150 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2527s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:45.808448501 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1111] 1 False 14.97
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1111'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1111', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3121318 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:51.191515363 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1321] 1 False 12.16
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1321'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1321', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3121922 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7585s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:50.173325372 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1080] 1 False 16.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1080'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1080', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3122415 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:56.589040115 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_651] 1 False 15.87
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_651'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_651', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3122416 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4141s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:56.162306242 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1193] 1 False 10.79
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1193'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1193', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3123855 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:56.295103618 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1737] 1 False 9.42
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1737'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1737', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-6' pid=3123890 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_641] 1 False 12.92
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_641'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_641', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3123914 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.714s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8781s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:58.494084605 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1565] 1 False 12.30
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1565'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1565', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-6' pid=3123984 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1060] 1 False 22.44
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1060'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1060', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3124055 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:08.503953622 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1040] 1 False 19.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1040'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1040', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3124335 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8806s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:06.892402412 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1687] 1 False 15.16
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1687'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1687', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3124337 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3642s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:02.805926315 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_826] 1 False 10.85
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_826'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_826', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3124391 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:34:58.730995253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1352] 1 False 13.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1352'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1352', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3124582 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6787s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:01.467709832 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1016] 1 False 17.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1016'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1016', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3125720 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:11.338998286 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1088] 1 False 13.75
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1088'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1088', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3126045 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:08.801914377 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_782] 1 False 21.91
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_782'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_782', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3126469 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:18.148249442 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1430] 1 False 14.17
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1430'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1430', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-7' pid=3126564 parent=3104035 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4132s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.40781s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.40788s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.40790s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.40792s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.40798s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.40812s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.40817s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1665] 1 False 10.87
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1665'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1665', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3127132 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.244s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:08.980607033 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1242] 1 False 15.69
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1242'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1242', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3127429 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6058s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6070s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:14.305642236 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1766] 1 False 16.71
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1766'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1766', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3127810 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8140s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1161] 1 False 22.00
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1161'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1161', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3128001 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12052s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:23.050944970 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1859] 1 False 15.59
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1859'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1859', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3128130 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:17.319513156 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1538] 1 False 16.72
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1538'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1538', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3128529 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_749] 1 False 8.55
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_749'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_749', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3129098 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1654] 1 False 18.06
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1654'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1654', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3129864 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:26.823133681 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_913] 1 False 11.78
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_913'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_913', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3129865 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2769s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:20.655892324 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1704] 1 False 15.34
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1704'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1704', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3130131 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:25.033561661 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1772] 1 False 21.24
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1772'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1772', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3130392 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7490s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:32.062386852 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1425] 1 False 12.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1425'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1425', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-8' pid=3130404 parent=3103351 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.616s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.99374s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.99386s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.99389s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.99392s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.99399s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.99421s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.99435s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1950] 1 False 21.38
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1950'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1950', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3130914 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:33.966041736 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_657] 1 False 14.77
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_657'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_657', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3131333 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3671s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:29.542794066 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1849] 1 False 16.32
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1849'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1849', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3131438 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3891s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:31.592284673 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1172] 1 False 14.54
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1172'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1172', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3131782 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:31.185707439 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_891] 1 False 13.64
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_891'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_891', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3131978 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5270s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:31.063337560 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_743] 1 False 16.83
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_743'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_743', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-8' pid=3132142 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_704] 1 False 17.21
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_704'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_704', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3132322 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:36.320266331 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1287] 1 False 12.92
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1287'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1287', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3132462 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:32.590696850 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1010] 1 False 18.70
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1010'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1010', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3132864 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3170s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:39.310088666 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1468] 1 False 14.55
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1468'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1468', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-8' pid=3133045 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1466] 1 False 16.42
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1466'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1466', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-8' pid=3133462 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8058s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8077s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.147740s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.147755s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.147758s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.147761s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.147769s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.147793s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.147810s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1098] 1 False 13.93
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1098'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1098', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3133480 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:37.071162292 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1230] 1 False 13.10
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1230'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1230', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3133916 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:38.159018036 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1033] 1 False 15.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1033'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1033', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3134044 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:40.671480085 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_649] 1 False 22.94
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_649'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_649', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3134331 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.612s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:49.915969280 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1769] 1 False 9.77
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1769'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1769', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-9' pid=3134431 parent=3103347 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.32393s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.32403s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.32406s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.32407s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.32411s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.32422s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.32430s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1731] 1 False 16.22
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-11' pid=3134936 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.77467s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.77478s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.77481s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.77484s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.77490s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.77514s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.77528s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1616] 1 False 15.53
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1616'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1616', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3135385 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:46.146656746 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_755] 1 False 19.69
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_755'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_755', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3135631 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1539] 1 False 8.91
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1539'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1539', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3136058 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3728s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1095] 1 False 24.09
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1095'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1095', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3136705 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:58.709164322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1808] 1 False 12.42
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1808'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1808', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3137877 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:51.864432808 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1851] 1 False 19.27
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1851'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1851', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3138123 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:35:59.990252120 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1440] 1 False 16.59
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1440'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1440', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-10' pid=3138207 parent=3103460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.563s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9032s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.101502s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.101518s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.101524s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.101527s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.101532s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.101557s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.101573s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1220] 1 False 18.23
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1220'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1220', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3138445 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:02.582990381 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1288] 1 False 13.17
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1288'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1288', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3139321 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:01.124622418 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1705] 1 False 16.69
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1705'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1705', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3139439 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:04.896810508 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1847] 1 False 16.23
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1847'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1847', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3139965 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7679s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7698s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:06.205153236 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1796] 1 False 12.31
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1796'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1796', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3140197 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:02.798948022 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1011] 1 False 17.69
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1011'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1011', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3140528 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:09.042594228 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1741] 1 False 10.21
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1741'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1741', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-10' pid=3140579 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1456] 1 False 8.90
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1456'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1456', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-10' pid=3140825 parent=3104127 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.67850s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.67857s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.67860s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.67862s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.67865s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.67878s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.67884s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1084] 1 False 11.88
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1084'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1084', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3141226 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7676s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:05.405230052 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_811] 1 False 16.70
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_811'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_811', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3141412 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:11.088191766 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1729] 1 False 17.05
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1729'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1729', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-10' pid=3141637 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1604] 1 False 20.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1604'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1604', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3141661 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3128s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3141s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:15.932880184 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_950] 1 False 10.51
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_950'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_950', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3141702 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:06.752828701 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_855] 1 False 16.57
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_855'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_855', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3142165 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:14.736436672 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1951] 1 False 18.23
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1951'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1951', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3142660 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:18.286271186 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1906] 1 False 17.52
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1906'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1906', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3142976 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:18.655935438 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_741] 1 False 16.51
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_741'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_741', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3143258 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1132] 1 False 14.46
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1132'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1132', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3143525 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:17.035594575 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1676] 1 False 13.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1676'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1676', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3143614 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:16.167946945 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_729] 1 False 9.75
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_729'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_729', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3143813 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.595s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1505] 1 False 12.91
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1505'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1505', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3144096 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_837] 1 False 20.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_837'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_837', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3144428 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:25.340198491 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_953] 1 False 20.18
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_953'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_953', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3144785 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:26.414911048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1126] 1 False 14.02
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1126'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1126', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3144873 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7305s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:20.806581648 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1711] 1 False 15.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1711'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1711', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3144950 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3349s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:22.624528491 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_935] 1 False 17.71
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_935'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_935', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3145186 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:26.786402911 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1897] 1 False 21.28
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1897'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1897', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3145506 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:32.452162968 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_931] 1 False 20.73
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_931'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_931', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3145987 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7527s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:33.775199523 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1374] 1 False 15.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1374'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1374', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-12' pid=3146068 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.31180s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31185s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31188s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31190s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31192s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31202s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31207s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.78346s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.78398s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.78414s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_747] 1 False 9.71
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_747'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_747', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3146307 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1093] 1 False 13.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1093'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1093', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3146466 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:28.169322021 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1444] 1 False 16.77
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1444'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1444', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-12' pid=3146794 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:32.055766329 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1493] 1 False 12.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1493'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1493', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3146971 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7962s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_829] 1 False 16.77
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_829'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_829', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3147221 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:33.769520727 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1662] 1 False 10.83
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1662'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1662', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3147333 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:28.410458714 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1568] 1 False 8.66
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1568'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1568', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-12' pid=3147599 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_909] 1 False 20.17
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_909'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_909', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3147598 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:38.540261578 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1790] 1 False 20.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1790'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1790', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3148188 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:41.068774935 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1014] 1 False 18.13
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1014'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1014', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3148241 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:39.119525839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1140] 1 False 13.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1140'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1140', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3148643 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:37.236011843 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_779] 1 False 22.48
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_779'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_779', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3148852 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9243s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:47.858744324 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1085] 1 False 20.58
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1085'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1085', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3149333 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:47.442270577 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1883] 1 False 12.31
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1883'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1883', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3149398 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:39.338741269 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1498] 1 False 19.33
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1498'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1498', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3149751 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1752] 1 False 17.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1752'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1752', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-13' pid=3149797 parent=3104127 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.65873s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.65882s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.65885s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.65887s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.65891s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.65904s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.65911s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1622] 1 False 11.89
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1622'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1622', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3149800 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
free(): invalid size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1021] 1 False 14.09
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1021'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1021', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3149906 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8676s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:42.749593751 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1908] 1 False 12.96
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1908'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1908', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3150248 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:43.045291869 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_630] 1 False 19.62
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_630'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_630', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3150781 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10558s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:52.123500819 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1694] 1 False 14.42
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1694'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1694', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3151019 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:48.236040092 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1744] 1 False 10.04
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1744'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1744', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-12' pid=3151020 parent=3103801 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1548] 1 False 20.57
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1548'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1548', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-14' pid=3151506 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8683s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1674] 1 False 12.99
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1674'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1674', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3151847 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:50.221618218 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1357] 1 False 8.72
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1357'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1357', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-11' pid=3152228 parent=3103727 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.60401s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60411s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60414s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60416s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60418s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60430s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60436s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.107833s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.107918s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.107931s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_748] 1 False 9.45
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_748'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_748', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3152481 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1099] 1 False 16.73
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1099'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1099', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3152521 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:55.965833242 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_683] 1 False 19.65
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_683'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_683', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3152577 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:59.033602843 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1355] 1 False 8.67
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1355'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1355', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-12' pid=3152739 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:48.228920337 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1644] 1 False 13.79
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1644'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1644', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3153136 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:36:54.911821922 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1455] 1 False 17.54
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1455'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1455', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-15' pid=3153443 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.73791s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.73797s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.73799s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.73802s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.73806s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.73820s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.73825s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1841] 1 False 15.44
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1841'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1841', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3154070 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7721s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:01.010976352 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1322] 1 False 15.99
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1322'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1322', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-12' pid=3154384 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:02.906128267 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_824] 1 False 18.76
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_824'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_824', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3155001 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:07.341408085 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1667] 1 False 15.66
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1667'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1667', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3155302 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:05.985479273 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_750] 1 False 15.70
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_750'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_750', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3155310 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1567] 1 False 16.07
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1567'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1567', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3155568 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1673] 1 False 12.17
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1673'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1673', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3155691 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6125s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:05.219823909 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_692] 1 False 11.39
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_692'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_692', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3156150 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:06.356267208 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1306] 1 False 20.29
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1306'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1306', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-15' pid=3156439 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.603s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:16.069446166 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1591] 1 False 9.58
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1591'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1591', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-14' pid=3156962 parent=3103801 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:06.903352847 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1647] 1 False 13.44
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1647'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1647', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3157191 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:12.447350361 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1924] 1 False 11.96
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1924'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1924', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3157229 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:11.009447298 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_724] 1 False 16.53
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_724'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_724', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-15' pid=3157498 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1764] 1 False 14.14
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1764'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1764', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-14' pid=3157506 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.40861s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.40871s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.40875s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.40877s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.40883s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.40915s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.40924s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1854] 1 False 23.35
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1854'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1854', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3157658 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8916s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:23.693727016 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_806] 1 False 13.33
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_806'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_806', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3157677 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:13.756747728 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_945] 1 False 16.26
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_945'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_945', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3157733 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:16.824489982 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_941] 1 False 16.87
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_941'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_941', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3158640 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3748s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3760s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:20.206783869 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1232] 1 False 13.33
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1232'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1232', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3158814 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2146s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:16.927576477 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1946] 1 False 19.00
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1946'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1946', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3159187 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:24.081263729 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1630] 1 False 17.81
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1630'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1630', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3159264 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.391s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7348s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_900] 1 False 22.94
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_900'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_900', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3159265 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7802s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:28.170345034 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1860] 1 False 18.78
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1860'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1860', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3159450 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:24.729412911 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1387] 1 False 16.60
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1387'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1387', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-17' pid=3159491 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:22.388826445 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_834] 1 False 12.17
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_834'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_834', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3159572 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:18.536205190 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1592] 1 False 9.14
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1592'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1592', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-15' pid=3159810 parent=3103335 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.105914s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.105930s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.105932s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.105934s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.105941s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.105963s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.105978s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1823] 1 False 15.88
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1823'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1823', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3159811 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3141s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:23.272290501 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1049] 1 False 16.58
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1049'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1049', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3159812 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:23.998145311 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1118] 1 False 14.18
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1118'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1118', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3159927 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:22.461181946 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1469] 1 False 11.75
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1469'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1469', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3160212 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7734s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1672] 1 False 15.86
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1672'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1672', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3160503 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:28.308586626 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1536] 1 False 12.56
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1536'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1536', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3161522 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.553s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1728] 1 False 16.88
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1728'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1728', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-16' pid=3161767 parent=3103351 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.62434s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.62441s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.62443s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.62450s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.62457s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.62475s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.62481s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1778] 1 False 15.10
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1778'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1778', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3161886 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.571s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:32.196464302 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1724] 1 False 17.19
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1724'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1724', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-17' pid=3162166 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.563s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_781] 1 False 19.69
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_781'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_781', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3162603 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:39.928693131 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1784] 1 False 13.42
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1784'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1784', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3162944 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3773s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:35.240746461 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1770] 1 False 16.70
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1770'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1770', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-14' pid=3163510 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1018] 1 False 12.80
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1018'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1018', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3163554 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:36.080156862 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1295] 1 False 21.61
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1295'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1295', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3163740 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:45.627693764 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1901] 1 False 13.53
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1901'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1901', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3163741 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:37.615203281 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1677] 1 False 15.76
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1677'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1677', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3163886 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:40.568525200 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1324] 1 False 13.00
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1324'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1324', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-16' pid=3164221 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8288s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 3.192293s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 3.192330s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 3.192333s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 3.192337s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 3.192343s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 3.192366s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 3.192376s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 3.239865s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 3.239976s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 3.239985s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1200] 1 False 15.63
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1200'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1200', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3164439 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:43.853631223 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1223] 1 False 17.91
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1223'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1223', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3164515 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:46.323651529 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1116] 1 False 24.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1116'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1116', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3165568 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:56.805143469 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1285] 1 False 11.98
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1285'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1285', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3166001 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3852s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:45.632512355 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1283] 1 False 12.56
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1283'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1283', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3166303 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:47.695240111 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1834] 1 False 22.47
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1834'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1834', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3166312 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:57.743924190 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1845] 1 False 19.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1845'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1845', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3166607 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:55.383202146 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1234] 1 False 21.16
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1234'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1234', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3166764 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6233s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:57.347584354 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1502] 1 False 17.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1502'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1502', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-17' pid=3167123 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.371s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5391s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_804] 1 False 18.42
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_804'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_804', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3167595 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6892s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:58.188792484 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1765] 1 False 12.35
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1765'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1765', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3167780 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4243s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1874] 1 False 12.66
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1874'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1874', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3168619 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:56.594483254 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1740] 1 False 7.95
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1740'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1740', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3169129 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_906] 1 False 14.04
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_906'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_906', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3169194 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6072s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:37:59.776509091 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1331] 1 False 14.12
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1331'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1331', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3169401 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:00.210848761 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_848] 1 False 14.38
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_848'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_848', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3169634 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5898s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:02.152099766 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1252] 1 False 10.28
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1252'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1252', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3170444 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6071s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:02.827983253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1540] 1 False 8.98
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1540'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1540', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-19' pid=3170528 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1394] 1 False 8.36
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1394'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1394', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3171555 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:02.856981490 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1574] 1 False 11.51
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1574'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1574', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3171718 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.251s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1519] 1 False 12.17
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1519'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1519', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3171784 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1391] 1 False 12.27
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1391'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1391', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3172095 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7202s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7220s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:08.408842590 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1779] 1 False 10.91
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1779'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1779', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3172226 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:07.501772258 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_639] 1 False 14.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_639'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_639', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3172369 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:10.929875926 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1454] 1 False 14.43
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1454'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1454', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-16' pid=3172910 parent=3103591 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.60537s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60547s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60550s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60552s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60556s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60567s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60576s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1487] 1 False 11.06
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1487'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1487', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-18' pid=3173291 parent=3104131 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.103187s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.103196s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.103198s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.103201s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.103205s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.103232s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.103245s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1050] 1 False 14.14
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1050'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1050', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3173358 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.198s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:14.678313304 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_859] 1 False 16.36
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_859'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_859', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3173692 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:18.018655288 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1009] 1 False 11.79
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1009'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1009', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3173771 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:13.613704004 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_845] 1 False 19.77
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_845'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_845', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3173772 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:21.667416347 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1426] 1 False 12.03
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1426'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1426', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-19' pid=3173846 parent=3103355 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.101652s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.101662s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.101666s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.101670s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.101677s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.101700s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.101714s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1437] 1 False 17.54
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1437'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1437', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3174019 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1103] 1 False 15.08
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1103'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1103', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3174551 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:22.018464439 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1188] 1 False 13.92
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1188'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1188', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3174911 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:22.071582899 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1209] 1 False 16.94
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1209'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1209', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3175066 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6700s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6723s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:25.779717840 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1246] 1 False 18.94
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1246'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1246', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3175508 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:29.887352779 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1715] 1 False 11.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1715'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1715', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3175600 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:22.725903251 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1074] 1 False 12.43
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1074'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1074', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3175967 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:25.075210963 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_762] 1 False 13.73
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_762'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_762', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3176269 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5715s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5738s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_903] 1 False 10.46
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_903'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_903', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3176435 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:24.778354853 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1788] 1 False 12.98
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1788'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1788', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3176545 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:27.675772593 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_778] 1 False 16.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_778'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_778', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3176994 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4239s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:34.389322516 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1836] 1 False 10.95
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1836'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1836', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3177845 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:31.418951970 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1954] 1 False 17.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1954'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1954', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3178296 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8004s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:39.285521321 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_822] 1 False 16.69
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_822'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_822', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3178349 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:38.179446905 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1213] 1 False 16.42
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1213'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1213', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3178473 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9563s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:38.080789208 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1599] 1 False 18.85
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1599'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1599', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-18' pid=3178611 parent=3103797 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] 0.54540s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.54557s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.54558s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.54560s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.54562s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.54572s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.54592s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:40.369042253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-18: tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1625] 1 False 9.28
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1625'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1625', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3178613 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:30.903978228 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1503] 1 False 16.72
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1503'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1503', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3179094 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1722] 1 False 13.36
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1722'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1722', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3179697 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8958s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:39.204216997 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1100] 1 False 16.86
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1100'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1100', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3179772 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:43.270639413 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1039] 1 False 12.62
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1039'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1039', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3179980 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7742s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:40.086671634 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1732] 1 False 11.83
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1732'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1732', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3180008 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6583s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1943] 1 False 15.39
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1943'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1943', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3180055 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7787s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:43.098849989 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1415] 1 False 16.39
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1415'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1415', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-21' pid=3180139 parent=3103394 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.68987s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.68997s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.69000s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.69002s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.69007s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.69025s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.69039s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1416] 1 False 11.22
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1416'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1416', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-18' pid=3180424 parent=3103899 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.95551s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.95561s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.95563s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.95566s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.95570s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.95600s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.95611s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_684] 1 False 17.33
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_684'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_684', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3180598 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:48.613318445 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1760] 1 False 9.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1760'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1760', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-20' pid=3181097 parent=3104127 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.52311s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.52320s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.52324s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.52327s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.52333s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.52356s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.52369s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1142] 1 False 14.07
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1142'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1142', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3181365 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:48.465560023 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1755] 1 False 16.14
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1755'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1755', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3181884 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_666] 1 False 20.80
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_666'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_666', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3182277 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4195s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:58.345139005 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1351] 1 False 13.82
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1351'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1351', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3182596 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:52.183163254 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_742] 1 False 11.84
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_742'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_742', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3182779 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9178s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1463] 1 False 9.88
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1463'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1463', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-23' pid=3183197 parent=3104035 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.137009s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.137022s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.137025s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.137029s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.137035s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.137064s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.137081s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1601] 1 False 11.48
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1601'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1601', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-19' pid=3183522 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1005] 1 False 23.97
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1005'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1005', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3183605 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:05.635734518 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_897] 1 False 16.89
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_897'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_897', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3183884 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:00.035752832 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_947] 1 False 17.63
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_947'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_947', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3183944 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8132s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8159s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:00.915634484 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1203] 1 False 12.34
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1203'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1203', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3184220 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:38:56.899389803 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1339] 1 False 18.01
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1339'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1339', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3184412 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:03.137992056 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_817] 1 False 13.69
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_817'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_817', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3185393 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:04.853207869 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1182] 1 False 21.34
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1182'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1182', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3185791 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:13.664295758 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1480] 1 False 11.86
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1480'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1480', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-22' pid=3185855 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.42s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1915] 1 False 17.84
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1915'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1915', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3185994 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:10.450958550 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1822] 1 False 14.81
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1822'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1822', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3186106 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:07.881472586 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1276] 1 False 19.56
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1276'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1276', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3186198 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7089s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7114s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:12.959028613 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1719] 1 False 14.94
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1719'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1719', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3186377 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:09.089429048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1457] 1 False 8.86
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1457'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1457', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-22' pid=3186522 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.97419s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.97443s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.97447s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.97452s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.97460s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.97479s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.97496s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1312] 1 False 13.93
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1312'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1312', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3186965 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:10.387607777 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1580] 1 False 9.04
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1580'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1580', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3187409 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1094] 1 False 18.98
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1094'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1094', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3187777 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:18.290055352 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1555] 1 False 10.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1555'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1555', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3188357 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_882] 1 False 11.84
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_882'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_882', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3188603 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:15.396120863 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1758] 1 False 14.14
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1758'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1758', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3188706 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_926] 1 False 17.47
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_926'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_926', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3188813 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7025s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:21.793967681 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_868] 1 False 10.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_868'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_868', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3188824 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7733s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:14.838941340 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1378] 1 False 15.37
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1378'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1378', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-22' pid=3188923 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:19.916428844 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1884] 1 False 18.71
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1884'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1884', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3189188 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:24.358328295 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_918] 1 False 14.74
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_918'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_918', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3189710 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:22.159253437 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1530] 1 False 17.28
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1530'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1530', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3190081 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_954] 1 False 13.00
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_954'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_954', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3190435 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:23.559078553 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1353] 1 False 12.38
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1353'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1353', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3190545 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:22.822832320 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_949] 1 False 13.85
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_949'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_949', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3191036 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3947s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:26.395175371 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_895] 1 False 20.23
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_895'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_895', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3191446 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3109s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:33.881241129 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1404] 1 False 14.99
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1404'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1404', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-22' pid=3191874 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1561] 1 False 14.75
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1561'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1561', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3191908 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1610] 1 False 603.00
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1610'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1610', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
> os.remove(f)
E FileNotFoundError: [Errno 2] No such file or directory: '/dev/shm/vashm_buff_k42qes_0'

test_tidl_unit.py:121: FileNotFoundError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6711s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:32.403066602 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_726] 1 False 11.74
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_726'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_726', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3192410 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1806] 1 False 14.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1806'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1806', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3192486 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:32.696190487 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1768] 1 False 9.93
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1768'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1768', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-23' pid=3192897 parent=3103513 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.69527s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.69538s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.69542s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.69544s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.69550s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.69575s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.69588s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1931] 1 False 13.72
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1931'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1931', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3193436 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10202s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:35.524071275 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1542] 1 False 14.78
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1542'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1542', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3193498 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1201] 1 False 15.91
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1201'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1201', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3193630 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:38.140742131 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_930] 1 False 18.58
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_930'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_930', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3194113 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:42.978229534 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1955] 1 False 13.29
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1955'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1955', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3194494 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:39.684336952 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1136] 1 False 17.74
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1136'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1136', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3195323 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6731s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:47.841355143 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1868] 1 False 16.45
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1868'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1868', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3195365 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:46.755754282 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1657] 1 False 16.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1657'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1657', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3195550 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:47.585075692 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_885] 1 False 16.89
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_885'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_885', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3196060 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.214s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:49.600132833 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1372] 1 False 14.57
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1372'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1372', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-23' pid=3196160 parent=3103591 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7135s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.54248s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.54255s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.54258s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.54262s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.54266s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.54284s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.54296s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.101079s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.101177s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.101189s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1842] 1 False 12.82
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1842'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1842', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3196281 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:46.750414932 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1008] 1 False 14.77
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1008'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1008', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3196744 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:51.414476068 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1020] 1 False 12.58
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1020'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1020', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3196927 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:50.172493357 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1810] 1 False 13.68
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1810'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1810', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3197066 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:51.874974412 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1855] 1 False 13.01
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1855'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1855', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3197493 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.38598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.38863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.38995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.39114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.39210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.39298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.39369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.39432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.39504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.39562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.39631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.39701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.39781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.39856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.39920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.40000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.40071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.40139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.40224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.40289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.40362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.40423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.40484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.40581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.40650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.40703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.40807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.40867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.40934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.41035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.41106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.41182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.41277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.41334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.41399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.41500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.41560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.41617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.41724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.41793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.41800s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.41814s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:52.497063833 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1038] 1 False 14.24
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1038'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1038', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3197565 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:53.840034217 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1388] 1 False 13.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1388'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1388', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3197605 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:52.617456465 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_752] 1 False 8.51
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_752'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_752', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3198818 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1362] 1 False 13.43
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1362'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1362', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-26' pid=3199342 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.68198s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.68213s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.68216s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.68219s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.68225s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.68252s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.68267s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.115665s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.115805s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.115819s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1664] 1 False 10.66
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1664'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1664', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3199701 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8104s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:39:57.370020565 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1238] 1 False 14.77
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1238'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1238', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3199705 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:01.550602178 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_740] 1 False 12.23
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_740'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_740', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3200028 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3242s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1179] 1 False 19.09
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1179'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1179', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3200610 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:08.842854735 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_828] 1 False 17.58
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_828'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_828', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3201087 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6819s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:09.051344332 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1659] 1 False 14.06
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1659'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1659', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3201505 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:06.668585501 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1004] 1 False 13.05
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1004'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1004', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3201764 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:06.668439417 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_951] 1 False 16.36
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_951'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_951', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3201891 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.167s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1887s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:10.343971564 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_774] 1 False 15.20
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_774'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_774', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3202093 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:10.729904801 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1097] 1 False 11.83
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1097'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1097', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3202246 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4271s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:09.282520747 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1336] 1 False 9.54
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1336'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1336', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-26' pid=3202993 parent=3104131 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.162s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.811110s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.811125s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.811127s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.811128s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.811130s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.811136s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.811140s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.867586s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.867651s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.867660s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1736] 1 False 9.96
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1736'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1736', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-27' pid=3204596 parent=3103355 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3305s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.41491s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.41505s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.41508s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.41511s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.41515s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.41541s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.41556s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_670] 1 False 11.67
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_670'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_670', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3204602 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:18.256405465 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1197] 1 False 12.73
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1197'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1197', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3205051 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:20.030972104 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_764] 1 False 8.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_764'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_764', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3205614 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1087] 1 False 12.52
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1087'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1087', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3205689 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:20.874332748 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1294] 1 False 20.40
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1294'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1294', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3205959 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:29.136530026 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_737] 1 False 14.24
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_737'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_737', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3205970 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.603s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1133] 1 False 11.55
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1133'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1133', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3206234 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:20.617370447 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1684] 1 False 20.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1684'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1684', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3206380 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:29.618484365 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_738] 1 False 8.61
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_738'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_738', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3206543 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1390] 1 False 14.22
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1390'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1390', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3206648 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9781s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:24.204842570 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1365] 1 False 8.60
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1365'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1365', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-28' pid=3206862 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.24181s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.24187s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.24189s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.24190s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.24193s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.24202s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.24208s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.72594s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.72696s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.72706s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1145] 1 False 11.56
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1145'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1145', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3206892 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:22.335545832 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1478] 1 False 16.73
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1478'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1478', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-28' pid=3206897 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.117917s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.117932s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.117935s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.117938s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.117943s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.117966s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.117975s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_899] 1 False 15.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_899'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_899', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3206989 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:26.342218411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_907] 1 False 15.33
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_907'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_907', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3207062 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7736s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:26.802583599 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1302] 1 False 15.47
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1302'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1302', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3207088 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:27.128359829 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_720] 1 False 11.69
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_720'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_720', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3207719 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:29.270658215 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1015] 1 False 16.33
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1015'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1015', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3208007 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:34.652707383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1227] 1 False 13.14
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1227'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1227', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3208091 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:31.749243498 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1569] 1 False 15.56
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1569'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1569', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3208273 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1838] 1 False 17.14
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1838'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1838', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3208470 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:37.236470152 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_673] 1 False 18.11
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_673'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_673', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3208585 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:38.745451951 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1186] 1 False 13.29
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1186'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1186', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3208695 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7810s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:34.737014369 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1393] 1 False 16.04
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1393'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1393', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3208869 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9159s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:38.113477867 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1120] 1 False 21.82
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1120'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1120', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3208982 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2679s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:44.871463799 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_780] 1 False 11.84
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_780'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_780', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3210323 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:38.957448417 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1643] 1 False 16.56
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1643'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1643', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3210476 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7635s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:44.157251849 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1165] 1 False 16.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1165'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1165', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3210805 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:45.275599336 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_905] 1 False 10.76
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_905'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_905', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3210907 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6156s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:40.035678572 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1047] 1 False 17.85
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1047'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1047', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3212043 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8718s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:52.365581460 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1077] 1 False 15.92
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1077'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1077', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3212156 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8787s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:50.624714017 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1571] 1 False 9.10
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1571'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1571', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3212200 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1041] 1 False 13.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1041'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1041', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3212251 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:48.503758501 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1563] 1 False 19.00
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1563'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1563', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3212773 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8005s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1767] 1 False 9.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1767'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1767', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3213177 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5076s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5091s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1886] 1 False 15.53
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1886'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1886', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3213241 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:53.937296252 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1036] 1 False 17.49
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1036'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1036', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3213295 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:56.089831332 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1497] 1 False 8.99
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1497'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1497', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3213350 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1130] 1 False 10.73
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1130'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1130', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3213371 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:49.505794684 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1939] 1 False 13.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1939'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1939', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3213427 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:52.332065067 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1605] 1 False 15.84
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1605'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1605', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3213716 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:55.581917755 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1821] 1 False 20.50
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1821'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1821', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3214067 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:02.264018187 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1511] 1 False 8.79
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1511'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1511', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3214717 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1462] 1 False 13.13
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1462'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1462', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-30' pid=3214803 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6906s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6935s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.85599s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.85606s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.85608s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.85611s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.85612s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.85627s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.85634s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1396] 1 False 16.72
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1396'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1396', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3214855 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7031s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:00.931407647 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_928] 1 False 11.80
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_928'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_928', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3215000 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:40:56.715641356 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_869] 1 False 19.07
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_869'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_869', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3215081 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6738s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:04.471831195 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1504] 1 False 12.11
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1504'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1504', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3215180 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1250] 1 False 15.60
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1250'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1250', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3215278 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:01.711084756 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1377] 1 False 13.10
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1377'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1377', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3215688 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:00.481956965 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_719] 1 False 15.07
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_719'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_719', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3215736 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8229s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:02.830906732 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1655] 1 False 18.63
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1655'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1655', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3215870 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2802s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2813s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:07.170604619 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_769] 1 False 8.63
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_769'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_769', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3216049 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1256] 1 False 15.62
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1256'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1256', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3216303 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:06.247488171 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_904] 1 False 11.68
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_904'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_904', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3216687 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:04.034622785 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1947] 1 False 13.85
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1947'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1947', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3216942 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:07.347514757 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1816] 1 False 12.47
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1816'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1816', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3217434 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3015s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:08.669336976 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1639] 1 False 19.61
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1639'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1639', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3217645 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:16.412274502 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_835] 1 False 21.80
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_835'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_835', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3217792 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:19.171742839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1524] 1 False 11.49
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1524'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1524', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3217915 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3604s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_846] 1 False 13.54
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_846'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_846', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3218055 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:11.784012717 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_711] 1 False 18.37
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_711'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_711', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3218897 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:20.608330901 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1899] 1 False 17.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1899'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1899', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3220059 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:24.179407006 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_879] 1 False 13.56
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_879'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_879', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3220109 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:20.795824211 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1513] 1 False 17.33
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1513'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1513', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3220177 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1418] 1 False 8.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1418'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1418', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3220536 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1607] 1 False 9.27
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1607'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1607', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3220696 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1680] 1 False 12.89
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1680'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1680', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3220974 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:23.127454895 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1149] 1 False 10.55
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1149'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1149', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3221339 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:22.381921639 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1251] 1 False 20.60
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1251'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1251', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3221465 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:32.850160900 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1576] 1 False 11.87
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1576'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1576', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3221832 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1658] 1 False 15.76
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1658'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1658', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3221917 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9153s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:30.828462243 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1202] 1 False 10.56
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1202'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1202', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3222238 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:26.900257393 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1180] 1 False 17.36
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1180'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1180', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3222255 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:33.769658270 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1293] 1 False 18.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1293'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1293', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3222504 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:35.181019478 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_851] 1 False 16.94
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_851'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_851', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3223234 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:36.162143057 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_699] 1 False 11.80
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_699'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_699', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3223811 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:32.149749968 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1957] 1 False 15.50
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1957'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1957', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3223917 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:36.162141946 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1602] 1 False 12.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1602'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1602', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-33' pid=3223971 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1593] 1 False 11.13
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1593'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1593', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3224108 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:32.179997007 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1279] 1 False 15.44
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1279'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1279', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3224195 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:36.957930321 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1410] 1 False 10.71
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1410'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1410', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-30' pid=3224361 parent=3103341 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.70887s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.70898s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.70900s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.70902s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.70906s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.70926s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.70938s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1174] 1 False 18.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1174'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1174', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3224741 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7645s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:42.466120230 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1217] 1 False 16.94
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1217'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1217', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3224956 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:42.454576070 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1257] 1 False 23.75
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1257'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1257', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3225562 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.144s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1667s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:52.741114190 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_849] 1 False 13.21
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_849'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_849', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3226589 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:45.674025094 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1460] 1 False 11.68
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1460'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1460', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-31' pid=3226803 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6155s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:44.385580968 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1368] 1 False 14.18
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1368'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1368', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-31' pid=3226822 parent=3103341 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.246s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.29688s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.29694s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.29696s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.29698s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.29701s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.29712s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.29718s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.74858s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.74906s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.74911s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_832] 1 False 19.56
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_832'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_832', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3226977 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:52.753722598 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_943] 1 False 17.42
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_943'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_943', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3227148 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8112s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:51.295901984 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_694] 1 False 17.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_694'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_694', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3227405 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:52.602892820 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1300] 1 False 12.94
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1300'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1300', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3227568 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6032s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:49.161370474 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_690] 1 False 15.91
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_690'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_690', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3227571 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2066s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:52.195472676 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1358] 1 False 8.86
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1358'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1358', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-35' pid=3229003 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5887s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.40329s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.40337s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.40339s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.40341s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.40346s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.40358s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.40365s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.86601s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.86668s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.86679s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1428] 1 False 6.98
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1428'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1428', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3229006 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5867s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1205] 1 False 13.60
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1205'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1205', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3229633 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:57.967223199 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1292] 1 False 8.96
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1292'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1292', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3229713 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:53.481424612 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1739] 1 False 6.99
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1739'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1739', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3229737 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1522] 1 False 6.53
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1522'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1522', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3230009 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1515] 1 False 13.50
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1515'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1515', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-36' pid=3230042 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3806s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_686] 1 False 15.04
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_686'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_686', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3230531 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:01.668274879 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1429] 1 False 7.49
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1429'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1429', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-32' pid=3230729 parent=3103341 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8930s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.96519s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.96537s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.96541s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.96544s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.96550s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.96583s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.96597s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1858] 1 False 10.54
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1858'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1858', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3231030 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:41:59.657413994 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1932] 1 False 13.98
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1932'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1932', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3231143 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:03.528831006 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_820] 1 False 16.25
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_820'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_820', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3231692 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:07.321091934 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_867] 1 False 21.60
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_867'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_867', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3232063 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:13.820387305 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_875] 1 False 12.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_875'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_875', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3232291 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:04.998397945 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1379] 1 False 19.26
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1379'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1379', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3232294 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:11.778974916 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1244] 1 False 15.42
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1244'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1244', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3232304 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6924s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:08.219989097 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1383] 1 False 8.37
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1383'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1383', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-37' pid=3232453 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.29994s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.30002s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.30003s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.30005s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.30009s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.30023s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.30030s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.77312s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.77357s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.77368s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1656] 1 False 15.85
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1656'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1656', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3232640 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:10.528185816 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1660] 1 False 13.32
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1660'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1660', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3232837 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:10.113235470 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1669] 1 False 18.49
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1669'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1669', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3233012 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:16.487917769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_938] 1 False 17.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_938'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_938', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3233431 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:17.030329749 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_823] 1 False 15.20
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_823'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_823', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3234058 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:16.896531178 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1510] 1 False 9.68
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1510'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1510', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3234162 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1547] 1 False 12.81
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1547'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1547', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3234173 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_702] 1 False 17.07
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_702'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_702', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3234310 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5864s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:19.238004613 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1253] 1 False 20.71
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1253'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1253', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3235007 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:25.813269397 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_735] 1 False 9.22
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_735'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_735', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3235021 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1514] 1 False 10.30
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1514'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1514', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3235443 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1865] 1 False 12.77
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1865'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1865', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3235527 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:20.399033142 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1546] 1 False 10.44
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1546'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1546', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3236137 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7871s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_901] 1 False 14.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_901'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_901', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3236211 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7909s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:24.863761892 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1127] 1 False 14.88
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1127'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1127', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3236787 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:26.969407002 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1405] 1 False 8.14
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1405'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1405', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3237199 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1628] 1 False 9.24
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1628'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1628', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3237529 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1799] 1 False 11.27
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1799'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1799', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3237642 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:26.413544469 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_818] 1 False 17.11
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_818'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_818', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3238042 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15535s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:33.622383537 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1523] 1 False 13.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1523'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1523', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3238404 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.608s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12087s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12121s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1063] 1 False 17.03
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1063'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1063', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3238623 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7242s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7263s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:35.562700047 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1309] 1 False 17.06
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1309'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1309', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-34' pid=3238728 parent=3104127 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5961s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.520428s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.520467s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.520471s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.520476s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.520481s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.520502s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.520512s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.568207s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.568282s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.568296s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_713] 1 False 19.04
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_713'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_713', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3238826 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.225s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:38.890276823 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1248] 1 False 13.09
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1248'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1248', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3238921 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:33.513829001 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1918] 1 False 17.67
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1918'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1918', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3239156 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:39.664203344 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1587] 1 False 16.03
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1587'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1587', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3239810 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.644s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1069] 1 False 11.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1069'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1069', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3240203 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6472s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:37.181451015 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_647] 1 False 10.45
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_647'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_647', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3240402 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:36.893652115 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1703] 1 False 21.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1703'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1703', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3240512 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:48.091010577 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1028] 1 False 9.76
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1028'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1028', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3240632 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:37.222715196 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1879] 1 False 14.61
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1879'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1879', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3240811 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:43.749238699 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1832] 1 False 15.24
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1832'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1832', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3240941 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8170s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:45.678661639 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1483] 1 False 13.95
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1483'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1483', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-37' pid=3241257 parent=3103338 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.96488s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.96500s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.96503s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.96506s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.96513s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.96538s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.96552s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1627] 1 False 13.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1627'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1627', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3242007 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:47.201480537 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1678] 1 False 16.20
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1678'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1678', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3242265 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3868s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3877s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:50.506826050 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_788] 1 False 16.00
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_788'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_788', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3242442 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:50.597104430 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1043] 1 False 13.77
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1043'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1043', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3242932 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:49.395971785 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1872] 1 False 18.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1872'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1872', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3243473 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:55.044185985 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_665] 1 False 12.50
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_665'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_665', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3243544 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:49.738412754 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_687] 1 False 11.66
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_687'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_687', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3244045 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:50.688782203 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1857] 1 False 21.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1857'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1857', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3244237 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7094s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7112s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:00.863033279 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1543] 1 False 9.59
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1543'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1543', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3244339 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4556s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1753] 1 False 10.27
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1753'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1753', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3244684 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3269s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1544] 1 False 16.78
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1544'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1544', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3245006 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1163] 1 False 19.03
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1163'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1163', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3245185 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8239s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:04.753875532 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_957] 1 False 14.87
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_957'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_957', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3245468 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2572s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:01.574591962 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1618] 1 False 7.98
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1618'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1618', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-36' pid=3245920 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1055] 1 False 14.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1055'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1055', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3246019 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:02.198545624 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_701] 1 False 11.90
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_701'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_701', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3246142 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:42:59.990129463 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1882] 1 False 20.05
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1882'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1882', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3246374 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:09.193015863 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_722] 1 False 15.32
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_722'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_722', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3246632 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2738s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1682] 1 False 14.86
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1682'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1682', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3246825 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:05.364352544 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1853] 1 False 12.62
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1853'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1853', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3247032 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:04.084925482 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1594] 1 False 9.17
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1594'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1594', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3247199 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1167] 1 False 19.13
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1167'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1167', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3247272 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:12.185341506 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1364] 1 False 12.01
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1364'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1364', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-37' pid=3247797 parent=3103712 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.60614s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60624s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60627s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60630s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60635s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60655s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60668s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.108829s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.108962s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.108976s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1488] 1 False 11.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1488'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1488', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3248048 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:08.028649962 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1406] 1 False 10.51
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1406'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1406', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3248203 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7087s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:07.633821611 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1106] 1 False 18.76
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1106'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1106', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3248911 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:18.808558002 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1803] 1 False 20.77
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1803'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1803', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3249100 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:21.715220620 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1675] 1 False 14.84
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1675'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1675', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3249482 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3574s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:16.968539525 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_676] 1 False 11.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_676'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_676', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3249559 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:13.334357265 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_874] 1 False 13.37
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_874'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_874', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3250134 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:17.460926840 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_703] 1 False 20.16
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_703'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_703', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3250249 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:24.599807322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1233] 1 False 17.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1233'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1233', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3250418 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6643s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:22.504944257 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_721] 1 False 23.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_721'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_721', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3250479 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:28.497908803 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1191] 1 False 18.40
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1191'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1191', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3250509 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3140s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:24.069384264 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1777] 1 False 18.42
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1777'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1777', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3250848 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2852s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:26.004583815 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1706] 1 False 11.22
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1706'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1706', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3251145 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4271s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:19.495628318 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1061] 1 False 10.29
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1061'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1061', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3251308 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:19.534852405 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_866] 1 False 13.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_866'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_866', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3251930 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:25.196936426 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1925] 1 False 18.56
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1925'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1925', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3252163 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:31.062647468 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_873] 1 False 12.16
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_873'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_873', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3252822 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:28.071791430 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1381] 1 False 10.29
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1381'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1381', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3253108 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3153s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:26.900477445 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1373] 1 False 16.06
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1373'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1373', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-38' pid=3253348 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.51721s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.51729s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.51732s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.51736s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.51740s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.51756s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.51766s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.98779s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.98886s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.98896s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_775] 1 False 14.33
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_775'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_775', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3253584 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5975s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:33.153991491 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1582] 1 False 10.27
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1582'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1582', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3253913 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1208] 1 False 16.03
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1208'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1208', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3253920 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:35.609500910 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1870] 1 False 14.64
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1870'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1870', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3254167 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:34.704487949 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1921] 1 False 16.13
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1921'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1921', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3254620 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:37.751457292 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1549] 1 False 8.77
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1549'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1549', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3255301 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1586] 1 False 9.72
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1586'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1586', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3255520 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_731] 1 False 13.97
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3255772 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1267] 1 False 12.81
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1267'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1267', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3256270 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:40.100604400 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_658] 1 False 16.09
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_658'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_658', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3257225 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:47.192187520 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1314] 1 False 14.74
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1314'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1314', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3257249 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:45.726305322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1577] 1 False 9.33
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1577'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1577', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3257776 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6874s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6889s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1756] 1 False 8.40
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1756'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1756', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3257905 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1081] 1 False 15.75
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1081'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1081', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3258077 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7471s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:50.021351450 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1229] 1 False 20.43
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1229'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1229', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3258225 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.156s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.159s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:55.129090541 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1259] 1 False 18.38
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1259'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1259', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3258366 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3242s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:54.024676997 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1495] 1 False 12.57
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1495'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1495', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-43' pid=3258494 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2745s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1048] 1 False 17.90
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1048'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1048', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3258952 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8088s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:57.310236931 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_771] 1 False 15.99
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_771'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_771', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3259007 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8825s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:55.658245895 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1212] 1 False 10.34
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1212'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1212', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3259108 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.74s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.76s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8801s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:50.482644285 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1431] 1 False 13.85
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1431'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1431', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-41' pid=3259712 parent=3103591 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.61621s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.61631s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.61635s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.61638s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.61642s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.61662s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.61675s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1811] 1 False 13.39
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1811'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1811', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3259850 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3005s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:55.933356852 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1067] 1 False 11.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1067'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1067', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3260277 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:55.349581148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1301] 1 False 13.85
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1301'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1301', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3260749 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8603s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:59.536527351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1433] 1 False 19.82
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1433'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1433', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3260766 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1589] 1 False 10.11
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1589'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1589', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3261065 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:56.363725538 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1746] 1 False 11.27
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1746'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1746', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-40' pid=3261211 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.31100s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31106s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31108s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31109s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31111s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31123s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31129s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_888] 1 False 15.54
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_888'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_888', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3261252 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:02.766024872 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_638] 1 False 12.74
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_638'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_638', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3261335 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:00.295687540 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1386] 1 False 8.54
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1386'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1386', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3261365 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3125s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:43:56.020466425 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1114] 1 False 17.71
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1114'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1114', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3261604 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9176s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9209s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:06.232504037 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1155] 1 False 18.29
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1155'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1155', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3261713 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:07.435537719 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_716] 1 False 13.95
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_716'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_716', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3261881 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:03.707385306 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1613] 1 False 14.27
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1613'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1613', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-43' pid=3261919 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] 0.91890s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.91909s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.91911s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.91914s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.91917s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.91929s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.91946s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:04.035871580 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-43:
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1356] 1 False 11.02
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1356'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1356', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-43' pid=3262032 parent=3103338 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8769s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.70933s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.70953s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.70957s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.70960s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.70965s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.70987s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.71002s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.118458s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.118585s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.118598s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1228] 1 False 16.81
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1228'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1228', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3263247 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:12.050430831 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1525] 1 False 14.70
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1525'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1525', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-42' pid=3263325 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6672s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1691] 1 False 12.17
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1691'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1691', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3263614 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:08.102615432 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1856] 1 False 18.15
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1856'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1856', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3263751 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:14.335555065 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_936] 1 False 18.91
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_936'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_936', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3263861 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7136s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:15.531641880 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1866] 1 False 17.17
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1866'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1866', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3264014 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:14.528202035 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1912] 1 False 14.26
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1912'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1912', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3264261 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7976s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:12.606098006 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_884] 1 False 17.13
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_884'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_884', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3264324 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:15.898045565 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1774] 1 False 15.44
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1774'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1774', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3264449 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:15.048077486 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1422] 1 False 8.52
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1422'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1422', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3264522 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1071] 1 False 14.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1071'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1071', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3264847 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:17.097245788 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_887] 1 False 19.51
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_887'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_887', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3265008 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7715s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:23.296236979 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1903] 1 False 16.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1903'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1903', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3265448 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:21.914687940 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1064] 1 False 14.22
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1064'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1064', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3266214 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:23.176309302 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1135] 1 False 13.43
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1135'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1135', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3266417 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4105s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:23.025323293 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1124] 1 False 13.74
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1124'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1124', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3266528 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.247s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:23.828216784 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1037] 1 False 15.97
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1037'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1037', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3267366 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:28.014139345 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_920] 1 False 14.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_920'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_920', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3267876 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7504s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:27.887593067 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1334] 1 False 11.97
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1334'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1334', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-43' pid=3268155 parent=3103460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5945s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.672423s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.672451s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.672455s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.672457s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.672464s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.672481s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.672491s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.718613s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.718692s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.718702s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_793] 1 False 15.06
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_793'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_793', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3268228 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:29.618855186 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1210] 1 False 17.04
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1210'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1210', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3268446 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:32.589656890 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1449] 1 False 10.56
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1449'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1449', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-44' pid=3268498 parent=3103351 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.112046s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.112051s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.112054s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.112056s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.112058s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.112065s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.112069s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1169] 1 False 9.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1169'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1169', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3269175 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:27.657756636 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_890] 1 False 12.46
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_890'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_890', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3269215 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:31.699082015 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1275] 1 False 20.15
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1275'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1275', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3269874 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:42.103927130 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1651] 1 False 15.07
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1651'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1651', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3270219 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:38.086663128 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1877] 1 False 19.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1877'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1877', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3270271 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:42.417558116 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1920] 1 False 20.59
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1920'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1920', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3270643 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:44.434001828 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_937] 1 False 20.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_937'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_937', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3270726 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6861s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:44.360533450 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1481] 1 False 14.65
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1481'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1481', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-43' pid=3270904 parent=3103899 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.114994s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.114999s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.115001s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.115004s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.115007s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.115017s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.115022s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_706] 1 False 11.74
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_706'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_706', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3271616 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:37.816523858 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1653] 1 False 16.92
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1653'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1653', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3271658 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:43.098020231 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_739] 1 False 13.77
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_739'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_739', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3271801 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1442] 1 False 15.25
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1442'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1442', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3272150 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:42.768571618 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1506] 1 False 15.11
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1506'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1506', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-46' pid=3272283 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5891s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_685] 1 False 11.74
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_685'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_685', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3272548 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:41.428059034 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1477] 1 False 13.84
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1477'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1477', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-47' pid=3272909 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.142845s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.142858s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.142862s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.142866s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.142871s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.142894s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.142906s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1922] 1 False 19.12
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1922'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1922', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3272998 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:51.786219606 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1354] 1 False 9.66
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1354'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1354', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-44' pid=3273679 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3806s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.30812s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.30823s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.30826s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.30829s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.30834s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.30860s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.30872s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.79463s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.79562s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.79577s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1062] 1 False 14.53
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1062'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1062', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3273993 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:52.453322825 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_661] 1 False 15.86
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_661'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_661', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3274092 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8093s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:53.911528023 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1315] 1 False 14.17
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1315'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1315', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3274433 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:53.128091517 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1046] 1 False 12.93
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1046'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1046', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3274893 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:53.449110673 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1801] 1 False 12.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1801'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1801', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3275172 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6838s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:53.778715488 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1885] 1 False 15.07
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1885'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1885', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3275422 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:57.169820568 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1867] 1 False 12.63
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1867'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1867', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3275550 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:55.061785619 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1862] 1 False 17.97
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1862'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1862', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3275944 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.624s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:01.786389025 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_650] 1 False 13.43
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_650'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_650', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3275992 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8980s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8998s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:44:57.369486172 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1286] 1 False 17.94
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1286'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1286', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3276089 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:02.382826145 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1844] 1 False 20.55
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1844'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1844', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3276090 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:05.020537054 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1512] 1 False 11.50
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1512'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1512', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3276091 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1507] 1 False 11.40
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1507'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1507', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3276626 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1557] 1 False 10.74
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1557'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1557', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-43' pid=3276821 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1934] 1 False 15.68
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1934'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1934', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3277076 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7116s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:05.256449586 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1199] 1 False 14.70
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1199'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1199', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3277625 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6778s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:06.573187829 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1451] 1 False 12.65
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1451'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1451', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-45' pid=3278147 parent=3103899 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6985s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.120249s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.120262s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.120265s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.120267s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.120272s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.120296s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.120309s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1509] 1 False 8.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1509'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1509', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3278178 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6152s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1486] 1 False 12.69
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1486'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1486', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3278329 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:06.258357454 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_809] 1 False 15.68
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_809'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_809', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3278614 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:10.726593377 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_689] 1 False 13.89
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_689'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_689', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3278843 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:09.886778916 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_858] 1 False 13.53
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_858'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_858', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3278936 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3054s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:10.049915102 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_807] 1 False 11.31
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_807'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_807', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3279138 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:08.775486873 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1743] 1 False 16.49
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1743'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1743', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3279185 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1695] 1 False 13.65
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1695'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1695', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3279706 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:12.949472517 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1850] 1 False 17.38
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1850'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1850', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3280377 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:18.983126717 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1554] 1 False 9.98
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1554'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1554', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-46' pid=3280617 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_940] 1 False 17.79
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_940'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_940', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3281339 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7128s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:23.087490317 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1089] 1 False 16.67
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1089'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1089', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3281605 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:22.860708955 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1154] 1 False 14.12
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1154'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1154', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3281664 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:20.706297277 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_800] 1 False 10.82
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_800'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_800', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3281766 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6035s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6049s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:17.535241579 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1953] 1 False 21.54
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1953'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1953', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3282176 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:30.327861324 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1187] 1 False 14.80
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1187'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1187', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3282387 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:24.762678782 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1893] 1 False 16.76
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1893'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1893', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3282471 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:26.960150383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1017] 1 False 14.00
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1017'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1017', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3282603 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:24.761942818 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1914] 1 False 11.66
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1914'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1914', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3282658 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:22.836087309 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1804] 1 False 14.43
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1804'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1804', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3282814 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:26.824920435 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1175] 1 False 13.54
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1175'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1175', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3282967 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6237s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6251s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:26.601470510 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1494] 1 False 12.56
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1494'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1494', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-48' pid=3283237 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9717s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1833] 1 False 17.93
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1833'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1833', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3283866 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:34.428173880 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_634] 1 False 19.47
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_634'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_634', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3283923 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:36.081205405 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1325] 1 False 11.28
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1325'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1325', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-49' pid=3284142 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.661367s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.661390s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.661393s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.661395s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.661399s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.661411s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.661417s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.707614s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.707716s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.707721s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1108] 1 False 16.77
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1108'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1108', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3284224 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7898s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:34.498747050 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1600] 1 False 9.45
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1600'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1600', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-46' pid=3284527 parent=3103712 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.593s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8239s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.81520s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.81530s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.81532s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.81534s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.81539s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.81551s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.81557s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_841] 1 False 13.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_841'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_841', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3285952 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:36.354189650 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1144] 1 False 13.82
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1144'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1144', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3286078 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:36.915230100 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1776] 1 False 15.45
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1776'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1776', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3286439 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5893s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:39.855101902 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1461] 1 False 12.87
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1461'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1461', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-48' pid=3286535 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:37.362833393 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1521] 1 False 12.03
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1521'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1521', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-48' pid=3286849 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1558] 1 False 9.85
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1558'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1558', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3286877 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1034] 1 False 10.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1034'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1034', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3286946 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9039s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:37.112141145 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_679] 1 False 12.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_679'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_679', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3286977 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:39.233896285 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1679] 1 False 15.76
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1679'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1679', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3287306 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4875s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:44.276566312 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_844] 1 False 18.79
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_844'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_844', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3288279 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2980s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2987s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:51.464789878 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_710] 1 False 18.53
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_710'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_710', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3288616 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:51.916990413 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1905] 1 False 13.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1905'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1905', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3288805 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:47.262161871 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1007] 1 False 15.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1007'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1007', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3289443 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:51.311061920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1614] 1 False 8.40
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1614'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1614', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-51' pid=3289631 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8749s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8766s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:44.341756012 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1720] 1 False 13.03
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1720'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1720', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3289869 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:49.886459236 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1231] 1 False 13.21
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1231'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1231', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3289971 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:50.248198621 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1685] 1 False 11.42
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1685'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1685', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3290050 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8297s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:48.540503648 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1532] 1 False 13.61
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1532'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1532', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3290348 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1448] 1 False 14.53
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1448'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1448', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-46' pid=3290502 parent=3103727 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.141291s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.141305s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.141308s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.141311s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.141317s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.141341s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.141354s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:53.395029213 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1818] 1 False 19.44
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1818'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1818', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3290507 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:58.823179213 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1900] 1 False 12.21
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1900'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1900', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3290587 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:51.803710398 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_852] 1 False 15.21
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_852'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_852', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3290588 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:54.864329892 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1873] 1 False 11.79
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1873'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1873', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3290670 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:51.899480418 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_825] 1 False 9.08
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_825'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_825', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3290825 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1919s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:52.462348383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1699] 1 False 8.61
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1699'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1699', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3290985 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.178s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:52.948301106 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1341] 1 False 11.38
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1341'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1341', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3291139 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:45:55.756535148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1713] 1 False 12.69
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1713'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1713', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3291824 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:00.024498172 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1590] 1 False 14.29
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1590'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1590', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3292228 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1281] 1 False 10.93
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1281'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1281', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3292797 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:01.133457961 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1748] 1 False 15.15
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1748'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1748', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-49' pid=3293092 parent=3103797 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8941s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.49504s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.49510s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.49511s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.49512s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.49515s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.49523s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.49529s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_921] 1 False 16.28
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_921'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_921', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3293229 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:07.162262302 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_672] 1 False 13.54
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_672'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_672', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3293583 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:04.844458306 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1278] 1 False 13.04
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1278'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1278', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3293698 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:04.545025385 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1450] 1 False 9.40
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1450'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1450', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-50' pid=3293873 parent=3103513 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.90581s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.90605s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.90607s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.90609s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.90614s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.90642s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.90656s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:01.093401429 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1434] 1 False 14.61
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1434'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1434', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3293878 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1407] 1 False 12.81
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1407'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1407', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-50' pid=3293879 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.102105s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.102131s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.102135s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.102139s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.102146s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.102167s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.102178s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1762] 1 False 14.83
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1762'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1762', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-50' pid=3294195 parent=3103351 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.71567s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.71576s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.71578s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.71581s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.71587s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.71608s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.71618s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1949] 1 False 19.14
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1949'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1949', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3294264 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:12.111418965 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1708] 1 False 17.67
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1708'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1708', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3294534 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7813s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:11.573477259 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1793] 1 False 17.96
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1793'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1793', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3294656 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:12.532614491 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1320] 1 False 18.73
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1320'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1320', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3294712 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7072s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1262] 1 False 15.04
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1262'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1262', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3294846 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:10.644033645 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_734] 1 False 16.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_734'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_734', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3295280 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1452] 1 False 11.13
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1452'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1452', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3295506 parent=3103338 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.94553s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.94563s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.94565s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.94567s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.94571s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.94586s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.94595s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1218] 1 False 17.24
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1218'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1218', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3295662 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8529s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:18.404836860 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_655] 1 False 12.12
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_655'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_655', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3295697 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.210s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:13.477027345 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1501] 1 False 16.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1501'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1501', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3296017 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1436] 1 False 8.87
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1436'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1436', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3296072 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.80261s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.80298s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.80301s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.80304s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.80309s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.80323s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.80337s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_878] 1 False 13.18
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_878'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_878', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3296091 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:16.019041610 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_892] 1 False 16.79
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_892'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_892', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3296348 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:21.329414500 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1447] 1 False 13.77
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1447'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1447', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-51' pid=3296382 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.123333s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.123342s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.123344s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.123347s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.123351s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.123370s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.123381s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_707] 1 False 10.58
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_707'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_707', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3296410 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.169s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.170s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:15.522642993 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1003] 1 False 10.26
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1003'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1003', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3296684 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:16.265458566 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1225] 1 False 13.63
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1225'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1225', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3296917 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.619s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:20.840168768 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_671] 1 False 11.01
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_671'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_671', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3297005 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:18.460395764 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1596] 1 False 9.52
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1596'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1596', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-51' pid=3297768 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.104229s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.104247s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.104252s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.104256s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.104261s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.104287s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.104300s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1277] 1 False 20.68
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1277'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1277', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3298144 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2788s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:32.304419021 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1289] 1 False 14.92
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1289'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1289', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3298168 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7967s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:26.581420647 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1941] 1 False 19.79
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1941'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1941', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3298474 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5062s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:32.431047721 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1389] 1 False 15.17
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1389'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1389', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3298794 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.36909s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.36918s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.36921s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.36923s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.36931s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.36955s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.36968s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.84680s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.84733s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.84744s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1929] 1 False 17.94
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1929'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1929', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3298896 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:31.648610122 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1360] 1 False 11.70
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1360'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1360', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3299133 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:26.169274404 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1240] 1 False 12.47
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1240'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1240', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3299400 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7892s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:28.049643993 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1122] 1 False 13.72
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1122'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1122', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3299459 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:29.552650462 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1878] 1 False 13.70
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1878'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1878', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3299520 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:29.790734711 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1399] 1 False 12.79
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1399'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1399', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-51' pid=3299567 parent=3103797 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.83094s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.83106s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.83108s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.83111s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.83115s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.83138s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.83147s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1641] 1 False 13.71
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1641'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1641', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3300164 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3669s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:32.163020345 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1045] 1 False 16.50
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1045'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1045', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3300165 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6816s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:34.978008172 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1311] 1 False 16.99
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1311'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1311', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3300268 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.154967s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.154986s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.154988s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.154990s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.154994s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.155008s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.155020s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.201795s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.201867s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.201878s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1910] 1 False 18.83
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1910'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1910', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3300572 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7738s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:39.050925732 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1928] 1 False 11.25
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1928'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1928', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3301566 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6038s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:37.797570306 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1491] 1 False 11.65
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1491'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1491', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3302042 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1196] 1 False 10.98
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1196'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1196', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3302115 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:39.292235369 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1603] 1 False 11.24
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1603'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1603', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3302655 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:40.485771672 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_698] 1 False 13.91
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_698'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_698', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3302874 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4165s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:44.989885948 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1400] 1 False 7.78
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1400'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1400', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-57' pid=3303272 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3854s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1261] 1 False 13.51
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1261'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1261', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3303366 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9028s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:45.821469985 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1435] 1 False 17.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1435'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1435', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3304372 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_648] 1 False 18.35
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_648'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_648', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3304554 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:53.801334814 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1446] 1 False 11.93
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1446'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1446', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3304907 parent=3103460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7770s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.100925s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.100937s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.100941s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.100943s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.100947s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.100968s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.100978s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1747] 1 False 14.67
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1747'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1747', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-51' pid=3305269 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
corrupted double-linked list
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1835] 1 False 11.46
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1835'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1835', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3305274 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2763s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2771s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:50.538085541 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1813] 1 False 13.24
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1813'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1813', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3305439 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7766s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:53.251156381 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1168] 1 False 12.32
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1168'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1168', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3305571 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:53.466627540 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_636] 1 False 14.60
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_636'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_636', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3306082 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:46:58.346616360 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1535] 1 False 11.71
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1535'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1535', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3306676 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1529] 1 False 13.56
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1529'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1529', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3306929 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.258s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1361] 1 False 11.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1361'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1361', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-55' pid=3307080 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.62492s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.62505s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.62508s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.62512s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.62517s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.62540s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.62553s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.109776s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.109817s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.109828s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1297] 1 False 17.74
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1297'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1297', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3307772 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2902s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:07.640342972 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1329] 1 False 20.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1329'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1329', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3308227 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:10.847053005 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_777] 1 False 19.37
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_777'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_777', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3308433 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:10.777578002 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1484] 1 False 14.54
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1484'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1484', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-53' pid=3308597 parent=3103712 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2839s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.69990s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.70004s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.70006s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.70009s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.70013s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.70038s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.70051s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_922] 1 False 17.04
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_922'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_922', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3308924 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5921s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:10.345972486 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1518] 1 False 11.60
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1518'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1518', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3309010 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1424] 1 False 17.94
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1424'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1424', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3309106 parent=3103347 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.74919s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.74927s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.74931s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.74934s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.74939s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.74959s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.74969s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1305] 1 False 11.67
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1305'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1305', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3309112 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:05.004182232 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1937] 1 False 19.80
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1937'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1937', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3309114 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:13.595518939 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1417] 1 False 9.63
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1417'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1417', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-51' pid=3309275 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3988s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_948] 1 False 16.58
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_948'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_948', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3309938 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:14.076864089 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1553] 1 False 10.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1553'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1553', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-54' pid=3310055 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1636] 1 False 15.74
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1636'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1636', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3310166 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:14.076881284 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1541] 1 False 11.39
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1541'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1541', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3310192 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_656] 1 False 18.25
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_656'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_656', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3310296 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:17.227168053 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1190] 1 False 15.07
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1190'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1190', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3310585 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6101s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:16.624754266 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1068] 1 False 13.06
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1068'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1068', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3310963 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:16.838011649 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1831] 1 False 17.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1831'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1831', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3311183 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:22.509704684 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1269] 1 False 17.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1269'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1269', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3311390 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9912s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:22.769386981 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1022] 1 False 11.53
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1022'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1022', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3311628 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.246s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:17.924006776 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1534] 1 False 12.11
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1534'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1534', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3311861 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_663] 1 False 21.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_663'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_663', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3312069 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:29.586480340 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1701] 1 False 12.08
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1701'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1701', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3312590 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9116s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:21.898888776 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1076] 1 False 18.94
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1076'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1076', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3312837 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:29.362906411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1904] 1 False 14.38
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1904'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1904', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3312912 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:25.189904082 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1096] 1 False 17.50
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1096'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1096', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3313256 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5910s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:29.531461711 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1840] 1 False 18.77
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1840'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1840', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3313603 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:32.427085211 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1830] 1 False 16.82
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1830'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1830', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3314516 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:33.461730821 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1887] 1 False 17.15
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1887'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1887', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3314606 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5698s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:34.123234925 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_850] 1 False 13.08
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_850'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_850', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3314681 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:30.455840942 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_760] 1 False 10.29
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_760'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_760', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3314780 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1245] 1 False 12.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1245'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1245', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3315597 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4842s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:34.233664809 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1631] 1 False 9.95
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1631'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1631', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3316939 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:37.041363111 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1027] 1 False 11.81
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1027'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1027', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3317004 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:39.265373791 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1526] 1 False 14.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1526'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1526', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3317940 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_794] 1 False 19.45
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_794'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_794', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3318047 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:48.955649414 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1896] 1 False 11.90
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1896'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1896', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3318430 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5898s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:42.342268149 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1489] 1 False 9.03
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1489'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1489', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-57' pid=3318520 parent=3103513 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.656s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.158883s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.158901s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.158904s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.158907s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.158912s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.158935s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.158952s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1326] 1 False 15.70
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1326'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1326', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-58' pid=3318884 parent=3103338 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.855148s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.855190s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.855193s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.855196s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.855202s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.855227s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.855237s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.906603s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.906897s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.906912s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1527] 1 False 18.02
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1527'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1527', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3319560 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1485] 1 False 11.12
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1485'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1485', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-58' pid=3319617 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_842] 1 False 13.27
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_842'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_842', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3320106 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:49.622067794 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1219] 1 False 13.02
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1219'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1219', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3320257 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7919s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:50.098561754 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1330] 1 False 12.73
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1330'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1330', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-58' pid=3320731 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:51.955291410 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1670] 1 False 18.83
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1670'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1670', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3320915 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:59.184765952 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1349] 1 False 11.88
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1349'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1349', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-57' pid=3321311 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:53.495234870 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1002] 1 False 13.02
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1002'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1002', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3321419 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:55.389128769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1092] 1 False 14.18
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1092'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1092', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3321503 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:56.854340514 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_802] 1 False 16.34
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_802'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_802', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3321691 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:59.824839735 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1876] 1 False 14.58
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1876'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1876', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3322105 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:59.969772089 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1395] 1 False 14.61
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1395'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1395', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3322179 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:00.085508694 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1110] 1 False 12.08
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1110'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1110', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3322789 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:47:59.418817360 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1652] 1 False 16.60
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1652'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1652', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3323045 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.619s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:04.806101046 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1176] 1 False 10.67
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1176'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1176', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3323449 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6121s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:00.318912646 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_792] 1 False 20.71
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_792'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_792', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3323540 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:10.873485749 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1156] 1 False 18.83
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1156'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1156', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3323955 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8121s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:10.884015144 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_730] 1 False 11.16
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_730'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_730', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3323961 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_813] 1 False 16.73
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_813'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_813', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3324192 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:10.042185301 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1139] 1 False 13.08
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1139'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1139', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3325203 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.608s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:10.080614604 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1578] 1 False 14.21
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1578'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1578', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3325546 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1632] 1 False 12.86
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1632'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1632', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3325824 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:11.711035589 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_956] 1 False 14.29
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_956'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_956', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3326327 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3139s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:14.109353994 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1812] 1 False 12.73
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1812'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1812', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3326384 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:12.657315665 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_669] 1 False 17.76
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_669'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_669', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3326392 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:17.756937240 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1420] 1 False 14.42
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1420'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1420', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3326467 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:14.498201604 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1635] 1 False 16.57
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1635'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1635', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3326480 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:16.940585015 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1917] 1 False 14.58
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1917'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1917', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3326600 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3140s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3153s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:15.468403802 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_732] 1 False 17.96
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_732'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_732', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-58' pid=3326766 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1492] 1 False 8.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1492'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1492', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-57' pid=3327123 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1572] 1 False 10.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1572'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1572', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3327308 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1412] 1 False 9.76
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1412'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1412', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-58' pid=3327404 parent=3103899 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.53257s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.53284s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.53288s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.53292s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.53298s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.53317s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.53328s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_654] 1 False 19.27
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_654'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_654', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3328204 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:27.525554451 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_767] 1 False 10.36
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_767'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_767', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3328658 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_910] 1 False 16.05
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_910'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_910', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3328915 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9135s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:27.011716054 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1909] 1 False 14.38
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1909'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1909', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3329152 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:26.067342596 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1815] 1 False 12.70
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1815'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1815', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3329315 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.610s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:24.841651417 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1474] 1 False 18.63
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1474'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1474', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-59' pid=3329413 parent=3103460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4795s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.99518s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.99530s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.99533s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.99535s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.99539s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.99558s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.99567s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1936] 1 False 16.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1936'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1936', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3329771 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:30.628266362 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1559] 1 False 11.40
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1559'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1559', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3330067 parent=3104035 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1926] 1 False 11.60
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1926'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1926', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3330317 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2807s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:27.104122981 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_642] 1 False 18.97
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_642'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_642', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3330544 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:35.756697687 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1829] 1 False 17.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1829'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1829', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3330763 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:35.135224847 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1942] 1 False 16.08
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1942'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1942', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3330977 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:35.478866773 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1458] 1 False 12.91
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1458'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1458', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-60' pid=3331233 parent=3103351 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.105964s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.105970s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.105972s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.105973s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.105976s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.105985s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.105990s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1837] 1 False 13.06
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1837'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1837', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3331648 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:36.766071806 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_733] 1 False 7.43
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_733'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_733', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-65' pid=3331931 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:32.206564045 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_924] 1 False 17.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_924'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_924', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3332366 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3970s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3988s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:43.367182681 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1150] 1 False 12.20
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1150'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1150', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3332848 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:39.295526819 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1318] 1 False 17.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1318'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1318', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-58' pid=3333130 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1121] 1 False 15.85
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1121'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1121', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3333175 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4947s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:43.516474169 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1363] 1 False 15.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1363'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1363', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3333398 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:43.765903046 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1432] 1 False 8.24
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1432'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1432', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3333486 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:37.073354567 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis free(): corrupted unsorted chunks
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1054] 1 False 11.58
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1054'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1054', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3333631 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:41.362195416 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1723] 1 False 12.78
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1723'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1723', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3334034 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:44.166955232 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_756] 1 False 19.10
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_756'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_756', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3334239 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1984s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1956] 1 False 17.90
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1956'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1956', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3334321 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.226s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:50.000327781 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1164] 1 False 12.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1164'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1164', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3334400 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:44.716293648 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1131] 1 False 12.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1131'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1131', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3334715 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:46.482955192 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1443] 1 False 14.17
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1443'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1443', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3334833 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1296] 1 False 15.13
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1296'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1296', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3335011 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:50.290123997 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1619] 1 False 12.10
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1619'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1619', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-60' pid=3335099 parent=3103797 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8815s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.147113s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.147165s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.147169s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.147171s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.147178s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.147199s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.147214s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:47.338980488 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-60:
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1304] 1 False 17.28
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1304'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1304', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-61' pid=3335174 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 3.340792s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 3.340826s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 3.340830s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 3.340834s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 3.340843s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 3.340866s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 3.340882s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 3.387919s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 3.387998s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 3.388009s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1800] 1 False 15.21
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1800'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1800', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3335269 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7773s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:51.267806635 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_761] 1 False 8.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_761'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_761', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3335452 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1408] 1 False 10.95
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1408'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1408', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3335567 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1328] 1 False 15.91
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1328'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1328', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-60' pid=3336025 parent=3103591 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 4.244266s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 4.244296s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 4.244299s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 4.244301s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 4.244306s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 4.244318s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 4.244324s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 4.291969s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 4.292083s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 4.292094s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1948] 1 False 14.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1948'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1948', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3336528 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8764s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:55.839501910 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1185] 1 False 14.48
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1185'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1185', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3336636 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:56.389144951 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1871] 1 False 11.93
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1871'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1871', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3337167 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:55.472614224 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1052] 1 False 17.22
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1052'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1052', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3337492 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:01.962941108 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1623] 1 False 9.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1623'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1623', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3337661 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1621] 1 False 10.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1621'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1621', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-63' pid=3337798 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6091s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1911] 1 False 13.34
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1911'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1911', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3337991 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:01.040005953 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1611] 1 False 10.35
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1611'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1611', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3338265 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6643s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:48:58.586223033 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1545] 1 False 15.54
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1545'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1545', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3338617 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1716] 1 False 16.48
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1716'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1716', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3338626 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:06.481209591 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1058] 1 False 18.05
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1058'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1058', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3338949 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:09.069044601 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1359] 1 False 10.57
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1359'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1359', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-63' pid=3339020 parent=3103513 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7852s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7870s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.54518s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.54527s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.54529s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.54533s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.54536s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.54559s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.54571s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.101072s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.101143s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.101157s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1754] 1 False 8.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1754'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1754', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3339463 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1157] 1 False 12.07
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1157'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1157', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3339826 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8768s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8787s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:07.391887511 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1710] 1 False 13.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1710'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1710', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3339950 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:08.901067480 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1500] 1 False 15.68
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1500'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1500', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3340199 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1620] 1 False 12.12
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1620'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1620', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3340738 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1814] 1 False 17.86
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1814'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1814', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3341155 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:18.954543646 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1609] 1 False 14.89
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1609'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1609', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3341386 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:16.411755622 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_705] 1 False 15.80
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_705'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_705', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3341443 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3676s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:17.586739392 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1345] 1 False 17.59
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1345'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1345', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-68' pid=3341511 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 5.810029s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 5.810049s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 5.810052s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 5.810055s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 5.810061s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 5.810076s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 5.810086s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 5.857144s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 5.857178s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 5.857184s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_629] 1 False 18.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_629'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_629', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3341640 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.250s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:20.533235471 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1598] 1 False 13.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1598'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1598', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3342818 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:19.368787276 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_717] 1 False 17.87
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_717'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_717', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3342819 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:24.232409489 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1024] 1 False 18.67
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1024'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1024', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3343047 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6178s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:26.087564596 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_797] 1 False 12.81
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_797'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_797', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3343380 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:21.720441897 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1945] 1 False 12.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1945'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1945', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3343427 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:21.366723494 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1249] 1 False 14.13
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1249'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1249', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3343465 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.229s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:23.403225263 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_695] 1 False 17.55
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_695'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_695', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3343580 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:27.675153949 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_952] 1 False 14.95
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_952'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_952', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3343906 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7861s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:26.223623790 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1761] 1 False 7.28
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1761'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1761', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3344476 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1402] 1 False 7.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1402'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1402', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-65' pid=3344474 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1380] 1 False 11.92
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1380'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1380', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-63' pid=3345391 parent=3103712 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.592s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.73857s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.73869s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.73873s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.73876s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.73880s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.73908s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.73920s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.121142s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.121239s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.121248s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1134] 1 False 24.27
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1134'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1134', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3345565 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.527899890 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1648] 1 False 12.62
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1648'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1648', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3345696 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:31.192524536 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1271] 1 False 14.24
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1271'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1271', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3346108 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:33.529692493 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_929] 1 False 14.06
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_929'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_929', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3346164 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.641s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:33.443267304 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1332] 1 False 13.02
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1332'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1332', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3346277 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:32.259024012 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1633] 1 False 21.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1633'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1633', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3346646 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.525926116 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1291] 1 False 21.43
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1291'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1291', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3346886 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.848341978 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_637] 1 False 19.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_637'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_637', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3347283 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.525557486 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_876] 1 False 16.08
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_876'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_876', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3347710 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.282460036 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1414] 1 False 9.07
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1414'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1414', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3347747 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_870] 1 False 16.35
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_870'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_870', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3347776 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.828067595 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1166] 1 False 14.55
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1166'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1166', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3347960 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:42.294068215 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1465] 1 False 9.65
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1465'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1465', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3348326 parent=3103712 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3906s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
free(): invalid size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1562] 1 False 8.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1562'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1562', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-63' pid=3348621 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3845s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1597] 1 False 8.92
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1597'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1597', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3348788 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_862] 1 False 10.68
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_862'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_862', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3349733 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:46.029388742 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1634] 1 False 8.76
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1634'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1634', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3350801 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11809s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:48.007854143 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_864] 1 False 10.59
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_864'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_864', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3350904 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:50.045686967 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_955] 1 False 21.71
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_955'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_955', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3351557 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:02.764499136 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1177] 1 False 11.06
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1177'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1177', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3351905 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:52.721696086 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1313] 1 False 13.92
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1313'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1313', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3352296 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:55.745105809 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1663] 1 False 11.75
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1663'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1663', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3352507 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:54.128143914 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_652] 1 False 22.07
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_652'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_652', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3352511 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.190s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:04.556790414 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_838] 1 False 21.47
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_838'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_838', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3352538 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:04.017530596 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1588] 1 False 8.46
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1588'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1588', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-66' pid=3352544 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.57849s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.57863s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.57866s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.57868s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.57872s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.57885s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.57893s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1479] 1 False 14.28
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1479'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1479', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-64' pid=3352650 parent=3103797 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5884s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.124468s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.124493s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.124497s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.124501s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.124505s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.124528s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.124541s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_927] 1 False 16.82
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_927'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_927', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3352758 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:49:59.697085016 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1798] 1 False 17.83
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1798'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1798', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3352905 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:01.252863552 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1137] 1 False 20.65
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1137'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1137', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3353034 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6186s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:04.728028898 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_812] 1 False 18.63
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_812'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_812', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3353195 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:04.145939447 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1105] 1 False 19.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1105'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1105', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3353361 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:05.310030808 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1013] 1 False 16.01
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1013'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1013', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3353671 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:04.149695088 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1236] 1 False 15.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1236'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1236', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3353742 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5731s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:03.894296852 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_946] 1 False 15.50
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_946'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_946', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3353897 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5257s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:05.657473752 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_916] 1 False 14.21
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_916'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_916', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3354097 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:05.228605820 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1078] 1 False 9.67
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1078'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1078', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3355111 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.187s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:05.807285762 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1550] 1 False 8.46
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1550'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1550', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-67' pid=3355741 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.191s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1690] 1 False 9.82
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1690'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1690', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3355935 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:08.242800824 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1935] 1 False 10.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1935'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1935', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3356311 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:09.750259946 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1032] 1 False 9.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1032'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1032', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3356503 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:09.268343729 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1206] 1 False 14.41
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1206'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1206', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3357151 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:15.634860341 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1385] 1 False 9.25
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1385'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1385', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-68' pid=3357152 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:09.998205540 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1237] 1 False 10.10
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1237'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1237', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3357705 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:12.753486697 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_640] 1 False 18.21
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_640'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_640', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3357778 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:21.331712710 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1890] 1 False 14.65
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1890'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1890', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3357958 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:18.279307903 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1807] 1 False 14.81
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1807'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1807', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3358105 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.69s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.69s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4082s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:18.630224274 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1583] 1 False 15.75
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1583'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1583', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3358140 parent=3103332 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1019] 1 False 18.87
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1019'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1019', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3358171 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:22.993643166 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1496] 1 False 17.14
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1496'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1496', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-65' pid=3358174 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1726] 1 False 11.02
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1726'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1726', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-72' pid=3358427 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.68451s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.68461s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.68465s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.68467s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.68471s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.68489s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.68505s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1464] 1 False 9.00
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1464'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1464', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-69' pid=3358529 parent=3104035 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.51145s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.51154s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.51155s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.51156s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.51159s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.51172s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.51178s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1059] 1 False 13.00
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1059'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1059', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3358580 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:17.807117794 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1714] 1 False 13.01
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1714'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1714', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3358698 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3527s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:18.294270480 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1473] 1 False 16.01
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1473'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1473', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-67' pid=3358714 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1453] 1 False 13.49
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1453'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1453', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3358924 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6141s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1366] 1 False 12.12
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1366'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1366', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3359062 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7798s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:17.615390101 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1189] 1 False 14.86
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1189'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1189', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3359539 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:23.148320646 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1698] 1 False 15.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1698'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1698', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3359652 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:24.135300552 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_785] 1 False 19.88
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_785'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_785', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3359810 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:29.756166767 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1564] 1 False 12.87
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1564'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1564', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3359872 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_925] 1 False 22.18
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_925'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_925', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3360464 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:36.045725201 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1717] 1 False 14.43
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1717'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1717', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3360701 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:30.049313795 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1919] 1 False 20.83
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1919'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1919', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3360741 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:36.554302716 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1763] 1 False 12.95
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1763'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1763', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3361094 parent=3103801 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1319] 1 False 12.89
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1319'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1319', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-68' pid=3361353 parent=3103335 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.584015s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.584044s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.584045s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.584046s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.584050s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.584062s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.584068s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.634246s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.634352s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.634365s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_833] 1 False 14.02
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_833'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_833', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3361449 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7026s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:33.103275708 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1376] 1 False 8.36
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1376'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1376', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-67' pid=3361561 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.58204s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.58216s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.58219s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.58221s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.58225s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.58252s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.58263s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.105358s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.105414s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.105428s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1123] 1 False 22.66
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1123'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1123', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3362027 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:43.988588327 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1759] 1 False 12.89
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1759'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1759', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3362366 parent=3103394 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2940s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2948s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_880] 1 False 16.27
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_880'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_880', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3362390 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3723s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:39.276089437 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1348] 1 False 17.11
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1348'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1348', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3362424 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7988s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:39.837904291 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_765] 1 False 16.13
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_765'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_765', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-67' pid=3362662 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1222] 1 False 17.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1222'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1222', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3363484 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:45.184795215 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1771] 1 False 8.06
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1771'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1771', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-65' pid=3364091 parent=3103727 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.54020s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.54025s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.54027s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.54029s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.54031s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.54040s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.54047s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_718] 1 False 14.91
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_718'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_718', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3364167 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:44.805427328 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_795] 1 False 16.88
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_795'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_795', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3364897 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:50.044336211 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1791] 1 False 20.21
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1791'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1791', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3365483 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:56.218452663 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_776] 1 False 16.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_776'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_776', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3365679 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:53.214342514 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_696] 1 False 13.04
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_696'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_696', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3365982 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:50.396179695 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_725] 1 False 8.01
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_725'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_725', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3366089 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1316] 1 False 19.69
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1316'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1316', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-68' pid=3366320 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 4.504365s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 4.504399s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 4.504402s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 4.504404s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 4.504409s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 4.504437s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 4.504451s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 4.550917s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 4.551000s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 4.551020s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1273] 1 False 12.78
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1273'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1273', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3366439 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:52.135053750 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1375] 1 False 14.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1375'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1375', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-71' pid=3366946 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7753s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:54.912131084 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1141] 1 False 13.20
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1141'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1141', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3367748 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7809s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:57.188047769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1898] 1 False 15.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1898'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1898', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3367940 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:00.028420073 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1727] 1 False 11.82
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1727'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1727', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-67' pid=3368351 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7691s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1629] 1 False 10.65
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1629'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1629', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3368474 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:56.573865857 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_796] 1 False 13.04
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_796'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_796', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3368894 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3567s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:00.725562975 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1482] 1 False 17.43
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1482'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1482', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-70' pid=3368945 parent=3103335 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.132091s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.132117s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.132120s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.132122s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.132125s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.132141s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.132149s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1817] 1 False 10.86
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1817'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1817', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3368969 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:50:58.763258671 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1940] 1 False 16.36
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1940'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1940', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3369020 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:04.373010699 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1335] 1 False 17.31
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1335'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1335', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3369436 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:07.071743455 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1031] 1 False 15.27
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1031'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1031', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3369543 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.55s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.57s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.589s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:05.677511334 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_688] 1 False 14.16
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_688'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_688', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3370011 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.559s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8951s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:06.384051983 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_805] 1 False 14.29
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_805'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_805', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3370416 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8032s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8062s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:07.985967830 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1671] 1 False 14.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1671'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1671', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3370481 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:07.985990197 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1397] 1 False 10.16
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1397'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1397', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3370781 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:05.313825605 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1828] 1 False 20.98
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1828'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1828', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3371030 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:17.237452049 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1718] 1 False 11.16
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1718'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1718', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3371432 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:08.360087800 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1531] 1 False 9.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1531'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1531', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-68' pid=3371612 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3891s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1162] 1 False 22.88
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1162'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1162', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3371921 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:21.663873222 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1797] 1 False 17.48
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1797'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1797', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3371949 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:16.528440351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1773] 1 False 14.74
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1773'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1773', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3372115 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4782s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:14.787257889 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1638] 1 False 16.06
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1638'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1638', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3372333 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11040s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:16.898199610 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1409] 1 False 10.99
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1409'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1409', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-31' pid=3373473 parent=3103801 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.100381s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.100389s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.100392s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.100395s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.100400s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.100421s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.100431s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_889] 1 False 10.99
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_889'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_889', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3373740 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:17.340356878 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1668] 1 False 20.06
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1668'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1668', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3373890 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:26.724206015 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1109] 1 False 14.46
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1109'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1109', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3373930 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:21.350857688 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1265] 1 False 15.40
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1265'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1265', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3374001 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3949s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:22.846430390 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1780] 1 False 12.79
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1780'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1780', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3374153 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.172s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:20.845774682 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1216] 1 False 13.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1216'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1216', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3374152 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:21.313620078 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1499] 1 False 11.39
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1499'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1499', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-67' pid=3374261 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1101] 1 False 21.58
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1101'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1101', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3374532 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:31.938820777 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1560] 1 False 10.68
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1560'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1560', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3375593 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1734] 1 False 14.66
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1734'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1734', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-71' pid=3375837 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name 0.61352s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.61388s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.61390s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.61397s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.61404s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.61425s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.61436s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1207] 1 False 12.22
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1207'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1207', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3375900 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7898s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:27.935159060 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1214] 1 False 13.38
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1214'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1214', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3376164 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:29.902110977 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1350] 1 False 10.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1350'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1350', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3376270 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:26.689887239 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1146] 1 False 21.27
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1146'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1146', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3376352 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:38.292123244 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_917] 1 False 14.52
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_917'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_917', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3376558 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9867s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:31.827359055 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1194] 1 False 15.53
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1194'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1194', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3376589 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:32.891357826 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1371] 1 False 13.59
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1371'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1371', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-68' pid=3377124 parent=3104127 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.65203s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.65213s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.65215s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.65217s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.65221s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.65240s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.65253s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.112561s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.112681s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.112696s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1528] 1 False 15.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1528'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1528', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3377268 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1035] 1 False 17.12
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1035'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1035', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3377311 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:38.027591908 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1809] 1 False 11.52
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1809'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1809', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3377461 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3580s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:32.962065668 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1584] 1 False 10.84
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1584'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1584', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3377584 parent=3103338 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
free(): invalid size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1792] 1 False 11.78
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1792'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1792', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3378333 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:37.248008973 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1707] 1 False 17.15
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1707'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1707', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3378334 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7100s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:42.612138083 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_773] 1 False 11.78
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_773'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_773', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3378580 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:38.537776369 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_942] 1 False 22.52
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_942'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_942', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3378604 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6125s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:49.511475066 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1745] 1 False 11.41
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1745'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1745', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-74' pid=3378640 parent=3103344 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.34769s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.34778s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.34782s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.34784s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.34789s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.34808s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.34818s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1280] 1 False 22.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1280'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1280', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3379032 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:51.017039247 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1224] 1 False 21.86
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1224'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1224', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3380043 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:53.637159413 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_784] 1 False 20.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_784'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_784', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3380367 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:53.048398259 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1688] 1 False 14.93
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1688'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1688', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3380559 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:48.000149102 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1880] 1 False 16.42
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1880'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1880', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3380561 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5892s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:49.545213749 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_693] 1 False 17.60
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_693'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_693', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3381019 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5006s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:52.174456839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1846] 1 False 14.56
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1846'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1846', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3381269 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:50.642475054 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1338] 1 False 15.10
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1338'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1338', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-33' pid=3381293 parent=3103801 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 5.658703s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 5.658725s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 5.658727s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 5.658728s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 5.658733s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 5.658747s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 5.658757s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 5.704566s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 5.704593s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 5.704600s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1183] 1 False 16.46
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1183'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1183', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3381523 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:53.719184611 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1192] 1 False 16.91
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1192'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1192', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3381747 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4588s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:54.891102788 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1927] 1 False 14.27
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1927'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1927', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3381791 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:52.405273215 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1573] 1 False 10.76
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1573'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1573', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3381849 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1566] 1 False 8.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1566'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1566', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3381877 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.229s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3017s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1843] 1 False 13.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1843'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1843', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3382086 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:53.618654795 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1888] 1 False 11.83
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1888'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1888', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3383456 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:58.314864768 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1826] 1 False 10.01
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1826'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1826', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3383969 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:51:57.891097310 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1445] 1 False 7.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1445'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1445', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3383971 parent=3103727 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1575] 1 False 7.62
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1575'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1575', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3384395 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_860] 1 False 14.21
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_860'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_860', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3384660 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:03.615723950 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1958] 1 False 14.38
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1958'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1958', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3385064 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7047s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:04.996091765 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1802] 1 False 18.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1802'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1802', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3385302 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6683s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:09.441794768 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1317] 1 False 24.82
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1317'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1317', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3385803 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:16.988855741 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1401] 1 False 14.15
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1401'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1401', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-75' pid=3385954 parent=3103338 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.75493s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.75498s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.75500s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.75501s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.75504s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.75515s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.75519s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1272] 1 False 14.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1272'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1272', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3386181 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:08.182755987 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1051] 1 False 21.62
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1051'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1051', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3386184 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.196s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:15.450886296 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1552] 1 False 12.11
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1552'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1552', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3386376 parent=3104127 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1370] 1 False 11.53
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1370'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1370', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3386602 parent=3103899 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:06.298277556 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1382] 1 False 13.10
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1382'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1382', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-74' pid=3387037 parent=3103591 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4371s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.30938s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.30943s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.30946s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.30948s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.30950s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.30959s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.30965s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.75846s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.75882s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.75886s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1692] 1 False 11.63
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1692'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1692', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3388510 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:17.985623174 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_798] 1 False 11.88
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_798'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_798', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3388588 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:18.373697441 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1346] 1 False 11.72
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1346'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1346', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-74' pid=3389317 parent=3103626 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 2.909643s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 2.909679s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 2.909683s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 2.909686s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 2.909692s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 2.909713s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 2.909725s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 2.958376s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 2.958472s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 2.958482s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1640] 1 False 10.36
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1640'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1640', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3389345 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:18.537956740 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1323] 1 False 12.91
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1323'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1323', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3390273 parent=3103355 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1785] 1 False 9.93
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1785'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1785', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3390396 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:21.232127993 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1173] 1 False 10.45
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1173'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1173', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3390572 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:22.555041462 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1148] 1 False 13.19
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1148'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1148', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3390873 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:25.886088433 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1284] 1 False 19.44
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1284'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1284', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3391218 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:32.930007279 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1735] 1 False 18.06
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1735'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1735', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-73' pid=3391684 parent=3104131 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.56722s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.56729s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.56733s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.56735s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.56739s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.56751s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.56759s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1441] 1 False 9.42
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1441'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1441', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3392091 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_766] 1 False 10.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_766'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_766', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3392096 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1581] 1 False 8.88
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1581'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1581', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3392209 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_772] 1 False 12.40
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_772'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_772', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3392516 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1210s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:30.462460111 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1255] 1 False 23.65
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1255'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1255', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3392840 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:42.196073148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1696] 1 False 16.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1696'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1696', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3393125 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:35.598187175 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1579] 1 False 12.42
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1579'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1579', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3393406 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1738] 1 False 18.17
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1738'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1738', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-80' pid=3393650 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_932] 1 False 12.69
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_932'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_932', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3393651 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:33.966092579 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1290] 1 False 19.17
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1290'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1290', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3393806 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:41.816910356 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1459] 1 False 12.87
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1459'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1459', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3394075 parent=3103355 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7884s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.137429s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.137444s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.137447s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.137451s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.137457s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.137483s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.137500s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1789] 1 False 15.42
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1789'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1789', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3394400 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.50s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:41.559635897 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1438] 1 False 10.94
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1438'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1438', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-75' pid=3394490 parent=3103359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.76054s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.76065s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.76067s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.76070s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.76077s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.76101s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.76121s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_754] 1 False 15.61
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_754'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_754', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3394642 parent=3103351 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1861] 1 False 12.98
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1861'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1861', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3395272 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7759s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:43.436042737 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1423] 1 False 10.79
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1423'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1423', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3395681 parent=3103626 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1472] 1 False 15.99
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1472'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1472', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3395763 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:48.209696856 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1369] 1 False 7.82
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1369'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1369', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3396000 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.26235s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.26242s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.26245s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.26246s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.26249s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.26259s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.26265s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.72286s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.72368s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.72378s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1158] 1 False 15.60
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1158'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1158', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3396202 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:49.049081347 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1266] 1 False 12.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1266'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1266', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3396385 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:46.192425693 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1661] 1 False 25.04
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1661'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1661', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3396765 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:00.802568121 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1247] 1 False 10.46
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1247'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1247', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3397174 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9006s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:47.559595808 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_632] 1 False 25.21
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_632'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_632', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3397181 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:02.268503122 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1891] 1 False 17.40
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1891'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1891', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3397345 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6748s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6769s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:54.915205096 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1697] 1 False 12.97
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1697'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1697', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3397346 parent=3103513 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:50.454516300 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1952] 1 False 19.87
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1952'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1952', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3397590 parent=3103347 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6676s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:58.415061399 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1551] 1 False 16.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1551'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1551', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3397693 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_853] 1 False 12.30
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_853'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_853', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3397783 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:52:51.855206371 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1517] 1 False 12.66
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1517'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1517', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-77' pid=3398352 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1848] 1 False 19.99
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1848'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1848', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3398443 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4941s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:02.267461155 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_914] 1 False 18.68
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_914'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_914', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3398582 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7241s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:01.628129564 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1863] 1 False 17.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1863'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1863', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3398696 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:00.881885566 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1646] 1 False 19.12
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1646'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1646', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3398752 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.210s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:02.585379969 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1556] 1 False 10.62
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1556'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1556', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3398975 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1115] 1 False 13.80
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1115'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1115', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3399191 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:01.484718955 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_831] 1 False 12.62
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_831'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_831', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3399719 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3967s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:01.763887056 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_919] 1 False 10.75
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_919'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_919', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3400327 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.174s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:02.637347226 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1107] 1 False 7.74
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1107'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1107', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3400979 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:02.302003260 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_736] 1 False 3.65
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_736'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_736', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-77' pid=3401131 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.2s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1237s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1626] 1 False 3.43
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1626'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1626', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3401202 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1537] 1 False 2.62
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1537'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1537', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3401668 parent=3103460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2586s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1520] 1 False 3.05
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1520'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1520', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3402087 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1344] 1 False 7.05
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1344'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1344', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3402217 parent=3103359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.146s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:05.208774595 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_865] 1 False 7.32
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_865'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_865', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3402247 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:05.938953990 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_681] 1 False 7.41
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_681'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_681', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3402625 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:06.974616225 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1944] 1 False 14.68
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1944'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1944', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3403179 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:15.312446427 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_843] 1 False 20.59
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_843'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_843', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3403351 parent=3103712 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4726s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:21.493650743 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1090] 1 False 13.61
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1090'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1090', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3403384 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6989s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:14.639405928 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1467] 1 False 13.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1467'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1467', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3403622 parent=3103347 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8922s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8948s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
free(): invalid size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1421] 1 False 16.48
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1421'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1421', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-79' pid=3403641 parent=3103355 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.55610s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.55627s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.55629s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.55631s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.55634s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.55647s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.55654s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1392] 1 False 9.95
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1392'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1392', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-77' pid=3403642 parent=3103335 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.62562s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.62569s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.62572s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.62576s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.62581s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.62601s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.62612s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.110298s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.110365s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.110375s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1795] 1 False 12.83
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1795'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1795', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3403768 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:14.434061800 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1113] 1 False 19.58
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1113'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1113', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3403855 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:21.192576381 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1427] 1 False 19.55
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1427'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1427', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3403959 parent=3104131 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1403] 1 False 8.83
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1403'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1403', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3404177 parent=3103964 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_939] 1 False 12.67
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_939'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_939', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3404203 parent=3103899 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2912s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:15.036942613 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1709] 1 False 20.61
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1709'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1709', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3404204 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:22.967789954 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1508] 1 False 16.45
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1508'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1508', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-83' pid=3404449 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_714] 1 False 13.28
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_714'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_714', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3404455 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:15.966946868 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1825] 1 False 16.92
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1825'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1825', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3404759 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:22.346903920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1585] 1 False 12.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1585'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1585', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3404796 parent=3103341 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:18.747528749 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_872] 1 False 18.06
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_872'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_872', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3404875 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:25.128454014 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1819] 1 False 14.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1819'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1819', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3405332 parent=3103964 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:26.037446314 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_646] 1 False 14.40
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_646'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_646', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3405434 parent=3103335 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:25.838108665 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_715] 1 False 15.68
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_715'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_715', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3406093 parent=3103394 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4854s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:30.097502498 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1730] 1 False 9.06
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1730'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1730', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-79' pid=3406264 parent=3103332 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.38774s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.38782s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.38784s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.38787s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.38791s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.38812s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.38822s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_674] 1 False 12.89
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_674'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_674', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3406407 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7921s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7937s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:28.348113679 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1310] 1 False 20.87
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1310'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1310', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-84' pid=3407344 parent=3103762 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== 3.205774s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 3.205800s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 3.205803s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 3.205805s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 3.205810s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 3.205833s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 3.205845s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 3.252222s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 3.252275s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 3.252286s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_728] 1 False 12.36
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_728'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_728', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-80' pid=3407409 parent=3103591 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_881] 1 False 21.04
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_881'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_881', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3407595 parent=3103727 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:41.133243543 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1681] 1 False 18.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1681'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1681', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3408063 parent=3104131 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7100s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7121s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:39.674632879 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1413] 1 False 13.85
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1413'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1413', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-79' pid=3408102 parent=3103712 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.60245s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60254s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60256s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60258s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60263s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60280s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60286s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1268] 1 False 21.14
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1268'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1268', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3408335 parent=3103359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:43.714570715 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1490] 1 False 15.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1490'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1490', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-82' pid=3408461 parent=3103513 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1239] 1 False 19.73
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1239'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1239', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3408716 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:43.881144013 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1894] 1 False 19.52
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1894'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1894', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3408917 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:44.703691058 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1347] 1 False 11.81
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1347'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1347', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3409177 parent=3103797 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:37.295780517 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1595] 1 False 12.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1595'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1595', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-81' pid=3409319 parent=3103964 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.136072s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.136085s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.136089s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.136091s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.136097s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.136119s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.136131s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1749] 1 False 19.51
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1749'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1749', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-77' pid=3410096 parent=3104127 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.31711s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31722s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31724s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31729s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31734s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31757s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31770s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_819] 1 False 14.08
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_819'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_819', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3410619 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:45.754222185 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1889] 1 False 12.64
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1889'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1889', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3410789 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:45.602949601 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1270] 1 False 17.00
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1270'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1270', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3411287 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8450s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:53.020412346 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_810] 1 False 15.62
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_810'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_810', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3411955 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:53.703743002 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1195] 1 False 19.31
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1195'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1195', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3412805 parent=3103338 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:59.314448207 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1615] 1 False 13.03
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1615'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1615', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-85' pid=3412806 parent=3103762 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:52.808451083 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false. malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1475] 1 False 8.79
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1475'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1475', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-79' pid=3413025 parent=3103727 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6701s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.91243s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.91254s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.91256s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.91260s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.91265s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.91286s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.91298s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1171] 1 False 17.52
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1171'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1171', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3413276 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8127s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:59.625940411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1307] 1 False 14.76
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1307'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1307', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-82' pid=3413564 parent=3103344 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:57.626753705 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1930] 1 False 15.67
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1930'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1930', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3413756 parent=3103332 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8214s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:59.634797613 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_861] 1 False 11.92
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_861'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_861', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-83' pid=3414003 parent=3103460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:53:56.634075297 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-83: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1384] 1 False 12.78
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1384'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1384', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-80' pid=3414085 parent=3103899 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.43620s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.43628s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.43631s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.43633s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.43637s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.43650s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.43656s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.90498s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.90543s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.90556s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_877] 1 False 14.53
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_877'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_877', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3414232 parent=3103355 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:00.149179133 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1721] 1 False 22.60
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1721'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1721', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3414267 parent=3103591 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:08.530093714 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1902] 1 False 14.57
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1902'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1902', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3414987 parent=3104127 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2989s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:02.912948204 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1781] 1 False 15.10
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1781'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1781', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3415136 parent=3103626 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6678s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:04.245563393 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1439] 1 False 8.93
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1439'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1439', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-81' pid=3415669 parent=3103394 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.83445s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.83458s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.83462s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.83464s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.83470s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.83493s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.83502s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_911] 1 False 18.46
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_911'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_911', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3415778 parent=3103341 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:10.150190094 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1787] 1 False 15.29
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1787'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1787', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3416184 parent=3103797 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:08.488865545 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_902] 1 False 15.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_902'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_902', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3416187 parent=3104035 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:08.488019143 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1025] 1 False 14.92
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1025'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1025', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-86' pid=3416204 parent=3103762 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:08.154683320 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-86: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_839] 1 False 13.23
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_839'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_839', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3416364 parent=3103351 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:07.098915780 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1471] 1 False 9.64
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1471'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1471', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-79' pid=3416581 parent=3104131 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2971s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.34160s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.34163s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.34164s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.34165s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.34167s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.34171s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.34174s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1159] 1 False 11.95
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1159'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1159', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-83' pid=3417268 parent=3103344 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.151s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:10.119305215 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-83: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_789] 1 False 10.35
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_789'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_789', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3417765 parent=3103801 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:10.150357911 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1342] 1 False 5.14
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1342'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1342', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-81' pid=3419452 parent=3103335 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:54:10.835564749 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_549] 1 True 11.35
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3217s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3242s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_307] 1 True 10.22
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.584s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_394] 1 True 17.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_235] 1 True 15.34
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3992s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4005s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_78] 1 True 19.76
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_682] 1 True 16.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1824] 1 False 15.04
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_303] 1 True 22.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_495] 1 True 10.84
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_594] 1 True 25.37
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_675] 1 False 22.68
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3087s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1875] 1 False 18.78
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.792s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9496s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_210] 1 True 15.76
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1298] 1 False 11.01
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3472s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_38] 1 True 13.60
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4930s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_266] 1 True 9.92
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1827] 1 False 20.87
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_26] 1 True 10.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.597s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_263] 1 True 18.22
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_215] 1 True 12.05
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_847] 1 True 20.67
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_102] 1 True 16.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.187s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_565] 1 True 11.60
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_241] 1 True 20.02
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_180] 1 True 13.37
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_302] 1 True 16.51
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3821s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1091] 1 False 23.05
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8852s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_254] 1 True 11.02
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3945s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_406] 1 True 19.06
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_915] 1 False 18.36
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8149s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_345] 1 True 23.60
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_181] 1 True 20.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7996s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_291] 1 True 17.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_568] 1 True 11.70
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_591] 1 True 15.67
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_79] 1 True 9.96
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1258] 1 False 12.35
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_368] 1 True 12.08
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_14] 1 True 14.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1235] 1 False 17.50
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_610] 1 True 14.04
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3968s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_274] 1 True 15.80
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3682s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_584] 1 True 12.87
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_481] 1 True 17.45
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5670s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_56] 1 True 16.21
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3583s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1147] 1 False 17.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_131] 1 True 14.87
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_599] 1 True 14.31
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_336] 1 True 12.59
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1211] 1 False 18.72
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_158] 1 True 15.48
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3978s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_445] 1 True 14.90
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6726s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_203] 1 True 22.76
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1057] 1 False 20.06
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_104] 1 True 19.71
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_388] 1 True 15.77
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_74] 1 True 16.59
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8594s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_51] 1 True 13.44
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_508] 1 True 15.22
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_390] 1 True 15.49
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_106] 1 True 13.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_437] 1 True 21.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_595] 1 True 16.82
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_117] 1 True 16.85
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_405] 1 True 13.82
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1023] 1 False 17.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.216s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_23] 1 True 17.07
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_177] 1 True 12.27
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8240s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_277] 1 True 15.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_2] 1 True 19.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6768s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_821] 1 True 18.63
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_108] 1 True 20.04
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1086] 1 False 12.72
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_149] 1 True 16.89
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_310] 1 True 12.49
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_598] 1 True 18.02
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_457] 1 True 10.54
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.234s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2510s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_667] 1 True 21.07
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_296] 1 True 20.89
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_172] 1 True 13.15
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_44] 1 True 12.00
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8066s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_300] 1 True 11.28
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_265] 1 True 18.66
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4017s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_67] 1 True 11.78
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.201s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_381] 1 True 15.36
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_186] 1 True 24.74
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_43] 1 True 19.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_6] 1 True 17.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_383] 1 True 11.76
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1198] 1 False 22.06
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_338] 1 True 13.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3708s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_361] 1 True 18.52
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1056] 1 False 17.17
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2531s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2543s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_70] 1 True 23.17
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4403s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_271] 1 True 11.54
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.578s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_222] 1 True 17.02
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7146s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_757] 1 True 12.56
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_573] 1 True 11.87
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3917s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_348] 1 True 11.11
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_483] 1 True 13.83
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_607] 1 True 13.81
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_744] 1 True 18.18
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8603s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28007533 bytes MEM: Free's : 26 free's of 28007533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_111] 1 True 14.24
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_421] 1 True 15.88
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_320] 1 True 15.06
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_105] 1 True 17.18
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_346] 1 True 11.47
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_883] 1 False 16.31
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_36] 1 True 16.94
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_306] 1 True 14.94
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_577] 1 True 11.28
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_471] 1 True 16.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_554] 1 True 15.74
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_475] 1 True 16.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_298] 1 True 15.39
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_535] 1 True 23.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_787] 1 True 16.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_97] 1 True 13.74
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9998s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_40] 1 True 22.15
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1805] 1 False 12.53
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8846s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_611] 1 True 20.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_12] 1 True 17.86
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_620] 1 True 13.47
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_545] 1 True 14.85
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_469] 1 True 14.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.238s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_597] 1 True 14.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_127] 1 True 18.32
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_786] 1 True 16.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3087s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_523] 1 True 12.65
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3927s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_373] 1 True 18.97
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_137] 1 True 17.62
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_139] 1 True 24.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_556] 1 True 17.50
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_768] 1 True 13.85
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_528] 1 True 21.85
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6810s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_283] 1 True 12.62
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_58] 1 True 12.78
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6782s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_612] 1 True 17.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_387] 1 True 15.58
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7398s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_82] 1 True 15.19
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_24] 1 True 14.15
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_206] 1 True 18.95
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_410] 1 True 15.96
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_193] 1 True 10.28
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_270] 1 True 14.14
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3104s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_529] 1 True 22.26
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_163] 1 True 19.48
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.587s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_449] 1 True 12.72
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2961s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_621] 1 True 18.85
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7529s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_98] 1 True 12.78
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_76] 1 True 14.03
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_197] 1 True 15.48
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_112] 1 True 15.82
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.167s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_622] 1 True 12.58
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3781s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3795s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_281] 1 True 17.55
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9110s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_143] 1 True 12.02
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_42] 1 True 15.89
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.251s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_10] 1 True 16.11
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4240s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4251s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1820] 1 False 13.92
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_478] 1 True 24.56
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_225] 1 True 18.98
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4102s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_308] 1 True 11.45
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7102s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_614] 1 True 20.88
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_244] 1 True 12.90
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.577s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_631] 1 True 18.54
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_392] 1 True 15.93
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_596] 1 True 16.34
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8178s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8209s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_697] 1 True 19.51
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_187] 1 True 16.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_572] 1 True 16.87
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_407] 1 True 15.95
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4962s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4975s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_5] 1 True 15.91
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_35] 1 True 13.92
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_397] 1 True 17.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8898s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_350] 1 True 16.28
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8870s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_324] 1 True 12.08
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_230] 1 True 25.05
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_4] 1 True 10.56
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_305] 1 True 15.90
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_590] 1 True 20.36
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_7] 1 True 20.65
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8944s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671785 bytes MEM: Free's : 26 free's of 18671785 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_213] 1 True 18.14
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_427] 1 True 18.49
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_325] 1 True 18.19
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9975s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_96] 1 True 14.41
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_208] 1 True 18.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.596s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_452] 1 True 15.06
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_415] 1 True 17.01
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_333] 1 True 15.03
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_466] 1 True 19.95
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_493] 1 True 25.31
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_318] 1 True 16.64
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_184] 1 True 17.16
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.590s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_20] 1 True 11.78
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4780s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_374] 1 True 16.60
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_420] 1 True 13.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_815] 1 False 16.81
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_615] 1 True 19.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7104s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_192] 1 True 15.90
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_182] 1 True 14.00
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_289] 1 True 15.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_288] 1 True 16.91
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6721s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_364] 1 True 13.98
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_304] 1 True 16.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9152s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_444] 1 True 20.04
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.574s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9567s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_261] 1 True 12.48
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_507] 1 True 13.37
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2859s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_162] 1 True 16.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.897s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_379] 1 True 13.95
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.590s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_161] 1 True 16.98
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_179] 1 True 14.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_224] 1 True 20.49
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_34] 1 True 20.18
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_243] 1 True 15.95
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_341] 1 True 18.14
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_356] 1 True 20.91
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_152] 1 True 17.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_349] 1 True 13.61
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7584s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_501] 1 True 18.33
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_273] 1 True 15.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3753s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_246] 1 True 14.23
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_49] 1 True 13.85
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_680] 1 True 17.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_539] 1 True 16.78
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_352] 1 True 11.56
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_422] 1 True 19.53
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8873s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_211] 1 True 15.67
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8771s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_219] 1 True 22.67
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4700s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_490] 1 True 13.41
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_103] 1 True 11.62
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4176s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_360] 1 True 25.19
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_176] 1 True 10.97
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1881] 1 False 16.13
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1006] 1 False 20.88
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_399] 1 True 20.74
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1184] 1 False 17.12
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6761s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_285] 1 True 18.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_678] 1 False 10.78
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1241] 1 False 15.68
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_712] 1 True 18.01
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5769s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_423] 1 True 11.34
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7749s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_533] 1 True 16.53
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1119] 1 False 16.32
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7868s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_840] 1 True 12.03
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_292] 1 True 10.47
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_604] 1 True 23.98
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_624] 1 True 15.65
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_677] 1 True 10.04
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_515] 1 True 21.51
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_467] 1 True 21.11
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_799] 1 True 15.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_402] 1 True 19.62
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7015s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1215] 1 False 20.01
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_509] 1 True 20.50
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_301] 1 True 18.12
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_205] 1 True 16.47
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_13] 1 True 14.42
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4139s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_484] 1 True 17.28
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_827] 1 True 14.86
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_561] 1 True 11.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_344] 1 True 11.33
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_154] 1 True 11.28
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.258s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_542] 1 True 9.10
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_61] 1 True 10.20
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.843s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_455] 1 True 13.31
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_645] 1 True 20.21
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6945s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_419] 1 True 17.72
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_196] 1 True 18.75
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1079] 1 False 14.76
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_322] 1 True 16.10
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_73] 1 True 21.89
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_299] 1 True 13.54
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_751] 1 True 12.51
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_448] 1 True 11.89
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_204] 1 True 11.90
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_516] 1 True 17.56
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3655s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_124] 1 True 16.57
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8980s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_218] 1 True 12.62
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_99] 1 True 19.77
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7945s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1070] 1 False 15.96
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_626] 1 True 12.64
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_418] 1 True 13.37
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_814] 1 True 16.22
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_527] 1 True 13.47
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_519] 1 True 14.86
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_9] 1 True 21.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.559s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8833s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_473] 1 True 15.95
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_57] 1 True 14.12
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_83] 1 True 15.86
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1689] 1 False 16.27
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4733s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_505] 1 True 18.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8800s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_506] 1 True 19.61
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_37] 1 True 11.62
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_312] 1 True 19.43
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_569] 1 True 13.91
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_429] 1 True 19.78
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_480] 1 True 19.31
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7969s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7989s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_279] 1 True 16.26
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_87] 1 True 11.89
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9873s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_552] 1 True 13.15
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1053] 1 False 17.16
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_520] 1 True 11.35
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_259] 1 True 20.76
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_128] 1 True 12.04
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3933s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_886] 1 False 11.45
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_511] 1 True 13.44
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7894s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_521] 1 True 23.91
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8450s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_433] 1 True 14.66
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8696s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_644] 1 True 20.51
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_403] 1 True 19.55
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_120] 1 True 12.89
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_29] 1 True 19.63
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1650] 1 False 15.50
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_125] 1 True 16.45
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_459] 1 True 19.98
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_575] 1 True 12.25
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4094s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_382] 1 True 17.62
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1221] 1 False 15.75
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5730s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1083] 1 False 13.97
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_309] 1 True 13.63
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.206s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_453] 1 True 13.03
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9909s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9935s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_653] 1 False 16.81
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8203s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_216] 1 True 15.98
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9044s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_745] 1 True 11.36
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_763] 1 True 10.89
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_228] 1 True 13.62
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2971s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_447] 1 True 19.60
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8919s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8937s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_80] 1 True 15.46
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_17] 1 True 22.95
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7039s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_201] 1 True 14.96
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6583s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_857] 1 True 23.39
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1015s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_68] 1 True 12.35
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1012] 1 False 16.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6823s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_267] 1 True 14.19
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_71] 1 True 14.96
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5768s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_141] 1 True 12.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_836] 1 True 19.19
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6975s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_151] 1 True 15.73
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_362] 1 True 15.03
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.43s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.570s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_489] 1 True 11.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_465] 1 True 20.52
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1102] 1 False 12.92
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_579] 1 True 17.68
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_413] 1 True 19.09
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5574s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_195] 1 True 13.74
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_253] 1 True 16.74
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1143] 1 False 20.53
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4349s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_367] 1 True 11.70
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8117s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_668] 1 True 14.52
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7813s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_347] 1 True 13.65
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_896] 1 False 12.05
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_233] 1 True 17.81
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_593] 1 True 13.00
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_746] 1 True 11.80
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8749s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8772s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_343] 1 True 16.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_371] 1 True 12.77
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1864] 1 False 19.52
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8784s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_791] 1 True 18.58
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6774s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_502] 1 True 18.70
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_494] 1 True 17.41
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8837s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8859s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_334] 1 True 18.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8527s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_450] 1 True 12.59
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_242] 1 True 17.06
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1029] 1 False 13.66
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_377] 1 True 11.53
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_482] 1 True 15.23
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_830] 1 True 18.40
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3887s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14584s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_585] 1 True 14.26
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_558] 1 True 12.17
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1153] 1 False 20.03
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7814s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7833s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_286] 1 True 10.76
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7691s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_400] 1 True 13.16
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_342] 1 True 15.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_133] 1 True 11.41
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1044] 1 False 16.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_92] 1 True 15.12
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_436] 1 True 13.89
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_517] 1 True 16.59
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_332] 1 True 13.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_603] 1 True 18.42
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_19] 1 True 13.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7056s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7082s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_856] 1 False 10.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_363] 1 True 14.01
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5563s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1282] 1 False 19.48
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_635] 1 False 21.24
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_69] 1 True 13.57
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_499] 1 True 19.63
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_77] 1 True 14.73
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_625] 1 True 15.18
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7645s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_540] 1 True 18.80
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_340] 1 True 15.85
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8263s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_209] 1 True 15.47
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6870s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_237] 1 True 16.68
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3945s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_643] 1 False 13.40
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5471s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_790] 1 True 14.18
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.224s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2215s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_551] 1 True 18.36
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_313] 1 True 12.31
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_48] 1 True 14.67
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_408] 1 True 11.81
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_417] 1 True 18.15
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_908] 1 False 17.94
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_231] 1 True 18.47
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_328] 1 True 13.61
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_52] 1 True 15.23
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_240] 1 True 12.76
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_168] 1 True 12.87
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_115] 1 True 18.62
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_619] 1 True 19.77
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_385] 1 True 14.97
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_544] 1 True 10.02
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_25] 1 True 13.44
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_256] 1 True 14.67
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6807s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_39] 1 True 12.07
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6700s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_121] 1 True 13.40
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_315] 1 True 11.99
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_898] 1 False 13.53
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2510s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_488] 1 True 14.54
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_223] 1 True 17.30
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_155] 1 True 10.51
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_351] 1 True 11.70
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.570s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10103s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_86] 1 True 10.19
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_443] 1 True 12.44
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_41] 1 True 17.94
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_588] 1 True 16.05
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_486] 1 True 19.64
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_175] 1 True 14.15
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_28] 1 True 18.25
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8083s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_335] 1 True 13.83
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_321] 1 True 14.90
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_474] 1 True 19.18
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1923] 1 False 14.59
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_803] 1 True 18.50
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_220] 1 True 16.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1152] 1 False 17.88
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1001] 1 False 12.53
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.907s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7147s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_214] 1 True 12.01
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7105s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_538] 1 True 12.00
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_339] 1 True 13.95
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_497] 1 True 17.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1852] 1 False 21.11
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_81] 1 True 13.84
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_496] 1 True 14.76
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_199] 1 True 18.77
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7679s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_559] 1 True 14.16
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_32] 1 True 12.00
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7221s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7243s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_430] 1 True 16.82
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_30] 1 True 19.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_546] 1 True 18.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_567] 1 True 18.74
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_11] 1 True 16.07
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_287] 1 True 12.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2933s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_532] 1 True 12.56
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_337] 1 True 17.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6817s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_278] 1 True 11.69
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_170] 1 True 13.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3857s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_247] 1 True 12.26
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_378] 1 True 12.33
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_816] 1 False 21.98
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_178] 1 True 20.44
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_660] 1 False 17.71
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_801] 1 True 18.04
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3678s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_138] 1 True 20.06
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_282] 1 True 14.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_101] 1 True 16.87
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8873s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_395] 1 True 11.60
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_431] 1 True 11.82
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_438] 1 True 22.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_190] 1 True 19.73
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3084s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3102s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_22] 1 True 16.59
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_94] 1 True 19.58
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_118] 1 True 12.53
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_60] 1 True 19.52
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_582] 1 True 12.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.251s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2928s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1178] 1 False 13.67
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_132] 1 True 17.62
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_330] 1 True 17.33
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_329] 1 True 16.55
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_64] 1 True 15.94
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_269] 1 True 18.10
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_536] 1 True 11.42
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_258] 1 True 11.99
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_89] 1 True 11.61
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4513s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_156] 1 True 20.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7584s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_252] 1 True 15.08
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_226] 1 True 17.20
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_727] 1 True 16.19
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_460] 1 True 19.00
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_530] 1 True 17.48
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6843s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_27] 1 True 17.74
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_414] 1 True 11.23
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_50] 1 True 19.02
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_412] 1 True 15.76
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_113] 1 True 17.31
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_319] 1 True 14.03
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_146] 1 True 16.34
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_194] 1 True 18.18
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7870s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7889s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_537] 1 True 13.93
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6870s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_359] 1 True 10.56
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7185s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_479] 1 True 15.58
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_434] 1 True 13.19
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_623] 1 True 19.53
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_262] 1 True 23.42
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4846s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_934] 1 False 12.87
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_255] 1 True 14.06
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4986s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_442] 1 True 17.75
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_659] 1 True 12.01
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_249] 1 True 15.79
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_580] 1 True 12.23
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_541] 1 True 17.65
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6961s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_297] 1 True 13.95
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_560] 1 True 19.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_245] 1 True 18.99
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2148s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_411] 1 True 13.08
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_589] 1 True 15.32
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_88] 1 True 19.73
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_525] 1 True 15.10
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_355] 1 True 13.22
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_323] 1 True 17.13
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_375] 1 True 17.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_357] 1 True 12.65
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5100s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1683] 1 False 11.24
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_126] 1 True 13.75
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6578s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_331] 1 True 11.11
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8513s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_454] 1 True 14.47
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9717s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9740s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1637] 1 False 10.95
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_491] 1 True 15.66
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_409] 1 True 12.47
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.592s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_140] 1 True 18.86
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_232] 1 True 11.90
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7263s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_463] 1 True 15.29
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6947s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_485] 1 True 11.73
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_294] 1 True 24.28
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.560s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8852s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1794] 1 False 23.65
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_370] 1 True 12.07
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6751s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6766s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_59] 1 True 10.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_174] 1 True 15.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_93] 1 True 12.79
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3205s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_239] 1 True 17.40
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_592] 1 True 16.22
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_606] 1 True 13.04
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_571] 1 True 16.27
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3088s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_425] 1 True 17.58
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_91] 1 True 11.50
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_257] 1 True 13.00
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_272] 1 True 18.79
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_66] 1 True 11.38
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1895] 1 False 13.00
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7263s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_144] 1 True 21.74
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_316] 1 True 16.45
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_311] 1 True 14.50
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_581] 1 True 11.57
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1160] 1 False 23.59
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2781s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_435] 1 True 18.30
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2791s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_55] 1 True 11.96
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_627] 1 True 17.07
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_217] 1 True 17.62
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.196s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_250] 1 True 13.98
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_166] 1 True 12.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1128] 1 False 15.12
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_227] 1 True 19.34
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6368s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_47] 1 True 16.18
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1892] 1 False 17.02
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_500] 1 True 14.81
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7185s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_608] 1 True 18.75
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13603s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_135] 1 True 11.25
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_116] 1 True 16.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1104] 1 False 12.46
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_236] 1 True 22.11
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7728s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1066] 1 False 19.03
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_440] 1 True 17.54
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_159] 1 True 14.93
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1264] 1 False 16.76
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2510s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_384] 1 True 16.60
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_142] 1 True 20.42
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8828s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8854s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1786] 1 False 16.00
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_275] 1 True 16.14
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1933] 1 False 11.30
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_33] 1 True 14.15
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_583] 1 True 16.86
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6719s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_164] 1 True 19.36
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7195s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7217s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_185] 1 True 11.59
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_464] 1 True 13.77
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_446] 1 True 16.15
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_8] 1 True 16.24
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_268] 1 True 13.71
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_157] 1 True 14.63
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_90] 1 True 13.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_574] 1 True 14.29
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3153s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_221] 1 True 16.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_191] 1 True 25.88
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3865s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3877s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_563] 1 True 23.66
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_167] 1 True 18.79
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_518] 1 True 21.98
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1783] 1 False 12.46
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7840s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_633] 1 True 21.30
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_424] 1 True 21.98
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_376] 1 True 20.44
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_770] 1 True 19.72
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_276] 1 True 15.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_130] 1 True 12.74
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_123] 1 True 13.04
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2510s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_404] 1 True 11.76
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1125] 1 False 10.48
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.162s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_570] 1 True 10.67
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9001s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_456] 1 True 18.43
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.567s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_564] 1 True 18.12
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_314] 1 True 17.61
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_477] 1 True 20.85
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_534] 1 True 21.07
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_458] 1 True 15.53
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_550] 1 True 19.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_238] 1 True 15.07
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_150] 1 True 11.94
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_326] 1 True 11.27
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_553] 1 True 12.16
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_183] 1 True 9.69
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8865s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_280] 1 True 22.23
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1702] 1 False 16.44
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_401] 1 True 19.12
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5906s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_110] 1 True 21.25
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_229] 1 True 20.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_260] 1 True 16.84
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_492] 1 True 19.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_72] 1 True 20.27
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_576] 1 True 12.68
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1204] 1 False 17.10
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_16] 1 True 12.91
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_616] 1 True 14.75
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7976s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_369] 1 True 17.71
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1243] 1 False 16.60
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_207] 1 True 11.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_531] 1 True 16.08
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_432] 1 True 17.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_284] 1 True 19.60
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3291s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_165] 1 True 16.68
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2866s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_609] 1 True 16.19
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.252s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.255s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_46] 1 True 12.16
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2763s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_264] 1 True 18.27
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7604s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_21] 1 True 13.39
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_122] 1 True 14.73
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5825s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_148] 1 True 18.64
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8113s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_426] 1 True 13.30
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_578] 1 True 16.43
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_31] 1 True 13.45
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8349s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671785 bytes MEM: Free's : 26 free's of 18671785 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_557] 1 True 22.83
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_487] 1 True 16.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_327] 1 True 19.04
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6795s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_451] 1 True 17.12
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1782] 1 False 20.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_358] 1 True 15.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_119] 1 True 17.26
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_84] 1 True 16.45
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_470] 1 True 16.88
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_75] 1 True 20.99
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_189] 1 True 21.53
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_504] 1 True 15.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_586] 1 True 19.86
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6813s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1] 1 True 20.84
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4768s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_63] 1 True 15.88
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1073] 1 False 18.17
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_602] 1 True 19.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_160] 1 True 13.14
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_618] 1 True 15.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_600] 1 True 18.56
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.631s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9471s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9500s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_295] 1 True 12.41
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_566] 1 True 19.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3005s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1026] 1 False 17.66
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_366] 1 True 19.82
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_153] 1 True 21.73
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_468] 1 True 17.61
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7038s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_617] 1 True 20.70
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_709] 1 True 15.86
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_462] 1 True 13.19
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_562] 1 True 10.60
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_100] 1 True 21.97
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_498] 1 True 12.04
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_386] 1 True 20.59
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7627s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_134] 1 True 19.51
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2577s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_365] 1 True 21.05
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_109] 1 True 19.91
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_753] 1 True 14.38
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1299] 1 False 21.64
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_202] 1 True 22.50
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2151s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_510] 1 True 16.02
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6807s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_62] 1 True 21.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1818s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_389] 1 True 15.89
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.167s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1170] 1 False 15.49
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_605] 1 True 14.80
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2263s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_45] 1 True 15.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.207s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_251] 1 True 14.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_512] 1 True 12.30
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_129] 1 True 11.80
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_428] 1 True 10.05
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2146s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2153s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_526] 1 True 10.80
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_3] 1 True 11.89
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_808] 1 True 11.82
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4670s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_293] 1 True 15.11
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5815s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_691] 1 True 20.81
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8419s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_396] 1 True 16.99
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_587] 1 True 15.47
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9052s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1138] 1 False 20.43
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_441] 1 True 19.40
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_547] 1 True 18.67
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_398] 1 True 13.44
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_476] 1 True 16.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_923] 1 False 14.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_700] 1 True 12.53
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5460s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_18] 1 True 14.99
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8791s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_514] 1 True 29.12
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8257s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_136] 1 True 28.11
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_524] 1 True 26.64
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2916s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_613] 1 True 24.04
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_372] 1 True 23.10
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_461] 1 True 20.61
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_15] 1 True 20.71
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_290] 1 True 19.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_200] 1 True 13.93
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.178s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_513] 1 True 11.78
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1916] 1 False 19.37
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1260] 1 False 12.84
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.572s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8009s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_65] 1 True 13.56
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_353] 1 True 20.48
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8047s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_522] 1 True 16.91
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.227s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_317] 1 True 23.38
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_145] 1 True 23.46
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7141s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7159s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_439] 1 True 16.41
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.559s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1129] 1 False 11.87
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6988s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_503] 1 True 15.16
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_114] 1 True 13.65
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_188] 1 True 12.68
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_380] 1 True 14.96
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_664] 1 True 15.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_354] 1 True 14.79
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_391] 1 True 15.03
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8204s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_555] 1 True 16.28
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_95] 1 True 17.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_662] 1 True 15.58
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6812s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_54] 1 True 11.61
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_171] 1 True 16.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_173] 1 True 18.94
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_248] 1 True 20.59
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7967s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_548] 1 True 15.78
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_85] 1 True 17.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1700] 1 False 17.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_212] 1 True 15.42
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1065] 1 False 15.62
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_601] 1 True 13.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_894] 1 False 14.49
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_169] 1 True 23.41
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7141s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_472] 1 True 15.02
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6088s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_234] 1 True 16.15
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_147] 1 True 18.90
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.175s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_393] 1 True 14.46
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7069s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7091s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_543] 1 True 15.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.246s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_416] 1 True 15.33
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_198] 1 True 11.23
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_107] 1 True 10.69
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_53] 1 True 10.76
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1250s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!